add peripherals
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 25 Jul 2018 03:47:00 +0000 (04:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 25 Jul 2018 03:47:00 +0000 (04:47 +0100)
36 files changed:
src/peripherals/bootrom/BootRom.bsv [new file with mode: 0644]
src/peripherals/clint/clint.bsv [new file with mode: 0644]
src/peripherals/flexbus/FlexBus_Types.bsv [new file with mode: 0644]
src/peripherals/jtagdtm/jtagdefines.bsv [new file with mode: 0644]
src/peripherals/jtagdtm/jtagdtm.bsv [new file with mode: 0644]
src/peripherals/jtagdtm/jtagdtm_new.bsv [new file with mode: 0644]
src/peripherals/sdram/bsvmksdram_model_wrapper.bsv [new file with mode: 0644]
src/peripherals/sdram/bsvmksdrc_top.bsv [new file with mode: 0644]
src/peripherals/sdram/controller/parallel_prog_delay_cell.v [new file with mode: 0755]
src/peripherals/sdram/controller/sdrc_bank_ctl.v [new file with mode: 0755]
src/peripherals/sdram/controller/sdrc_bank_fsm.v [new file with mode: 0755]
src/peripherals/sdram/controller/sdrc_bs_convert.v [new file with mode: 0755]
src/peripherals/sdram/controller/sdrc_core.v [new file with mode: 0755]
src/peripherals/sdram/controller/sdrc_req_gen.v [new file with mode: 0755]
src/peripherals/sdram/controller/sdrc_top.v [new file with mode: 0755]
src/peripherals/sdram/controller/sdrc_xfr_ctl.v [new file with mode: 0755]
src/peripherals/sdram/sdr_top.bsv [new file with mode: 0644]
src/peripherals/sdram/tb_bsv_wrapper.bsv [new file with mode: 0644]
src/peripherals/sdram/tb_top.bsv [new file with mode: 0644]
src/peripherals/tdm/TCM.bsv [new file with mode: 0644]
src/peripherals/vme/Memory_vme_16.bsv [new file with mode: 0644]
src/peripherals/vme/Memory_vme_32.bsv [new file with mode: 0644]
src/peripherals/vme/Memory_vme_8.bsv [new file with mode: 0644]
src/peripherals/vme/vme_defines.bsv [new file with mode: 0644]
src/peripherals/vme/vme_master.bsv [new file with mode: 0644]
src/peripherals/vme/vme_parameters.bsv [new file with mode: 0644]
src/peripherals/vme/vme_top.bsv [new file with mode: 0644]
src/uncore/axi4/SlaveWrapper.bsv [new file with mode: 0644]
src/uncore/debug/DebugModule.bsv [new file with mode: 0644]
src/uncore/debug/RBB_Shakti.bsv [new file with mode: 0644]
src/uncore/debug/RBB_Shakti.c [new file with mode: 0644]
src/uncore/debug/RBB_Shakti.h [new file with mode: 0644]
src/uncore/debug/defines.bsv [new file with mode: 0644]
src/uncore/tilelink/TLMemoryMap.bsv [new file with mode: 0644]
src/uncore/tilelink/Tilelink.bsv [new file with mode: 0644]
src/uncore/tilelink/Tilelink_Types.bsv [new file with mode: 0644]

diff --git a/src/peripherals/bootrom/BootRom.bsv b/src/peripherals/bootrom/BootRom.bsv
new file mode 100644 (file)
index 0000000..cd67f37
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+Copyright (c) 2013, IIT Madras
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+*  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+*  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+*  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+package BootRom;
+       import defined_types::*;
+       `include "defined_parameters.bsv"
+       import BRAMCore :: *;
+       import DReg::*;
+       import Semi_FIFOF        :: *;
+       import AXI4_Types   :: *;
+       import AXI4_Fabric  :: *;
+       import BUtils::*;
+       import axi_addr_generator::*;
+
+interface BootRom_IFC;
+       interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
+endinterface
+typedef enum{Idle,HandleBurst} Mem_state deriving(Bits,Eq);
+(*synthesize*)
+module mkBootRom (BootRom_IFC);
+
+       // we create 2 32-bit BRAMs since the xilinx tool is easily able to map them to BRAM32BE cells
+       // which makes it easy to use data2mem for updating the bit file.
+       BRAM_PORT#(Bit#(13),Bit#(32)) dmemMSB <- mkBRAMCore1Load(valueOf(TExp#(13)),False,"boot.MSB",False);
+       BRAM_PORT#(Bit#(13),Bit#(32)) dmemLSB <- mkBRAMCore1Load(valueOf(TExp#(13)),False,"boot.LSB",False);
+
+       AXI4_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE)  s_xactor <- mkAXI4_Slave_Xactor;
+
+       Reg#(Mem_state) rd_state <-mkReg(Idle);
+       Reg#(Mem_state) wr_state <-mkReg(Idle);
+       Reg#(Bit#(8)) rg_readburst_counter<-mkReg(0);
+       Reg#(AXI4_Rd_Addr       #(`PADDR,`USERSPACE)) rg_read_packet <-mkReg(?);
+       Reg#(AXI4_Wr_Resp       #(`USERSPACE)) rg_write_response <-mkReg(?);
+
+       rule rl_wr_respond(wr_state==Idle);
+      let aw <- pop_o (s_xactor.o_wr_addr);
+      let w  <- pop_o (s_xactor.o_wr_data);
+          let b = AXI4_Wr_Resp {bresp: AXI4_SLVERR, buser: aw.awuser, bid:aw.awid};
+               rg_write_response<=b;
+               $display($time,"\tBootROM: Illegal Write operation on BootROM");
+               if(aw.awburst!=0)
+                       wr_state<=HandleBurst;
+               else
+               s_xactor.i_wr_resp.enq (b);
+       endrule
+
+       rule rl_wr_burst_response(wr_state==HandleBurst);
+      let w  <- pop_o (s_xactor.o_wr_data);
+               if(w.wlast) begin
+                       wr_state<=Idle;
+               s_xactor.i_wr_resp.enq (rg_write_response);
+               end
+       endrule
+
+       rule rl_rd_request(rd_state==Idle);
+               let ar<- pop_o(s_xactor.o_rd_addr);
+               rg_read_packet<=ar;
+               Bit#(13) index_address=(ar.araddr-`BootRomBase)[15:3];
+               dmemLSB.put(False,index_address,?);
+               dmemMSB.put(False,index_address,?);
+               rd_state<=HandleBurst;
+               `ifdef verbose $display($time,"\tBootROM: Recieved Read Request for Address: %h Index Address: %h",ar.araddr,index_address);  `endif
+       endrule
+
+       rule rl_rd_response(rd_state==HandleBurst);
+          Bit#(`Reg_width) data0 = {dmemMSB.read(),dmemLSB.read()};
+      AXI4_Rd_Data#(`Reg_width,`USERSPACE) r = AXI4_Rd_Data {rresp: AXI4_OKAY, rdata: data0 ,rlast:rg_readburst_counter==rg_read_packet.arlen, ruser: 0, rid:rg_read_packet.arid};
+               let transfer_size=rg_read_packet.arsize;
+               let address=rg_read_packet.araddr;
+               if(transfer_size==2)begin // 32 bit
+                       if(address[2:0]==0)
+                               r.rdata=duplicate(data0[31:0]);
+                       else
+                               r.rdata=duplicate(data0[63:32]);
+               end
+      else if (transfer_size=='d1)begin // half_word
+                       if(address[2:0] ==0)
+                               r.rdata = duplicate(data0[15:0]);
+                       else if(address[2:0] ==2)
+                               r.rdata = duplicate(data0[31:16]);
+                       else if(address[2:0] ==4)
+                               r.rdata = duplicate(data0[47:32]);
+                       else if(address[2:0] ==6)
+                               r.rdata = duplicate(data0[63:48]);
+      end
+      else if (transfer_size=='d0) begin// one byte
+                       if(address[2:0] ==0)
+                 r.rdata = duplicate(data0[7:0]);
+               else if(address[2:0] ==1)
+                 r.rdata = duplicate(data0[15:8]);
+               else if(address[2:0] ==2)
+                 r.rdata = duplicate(data0[23:16]);
+               else if(address[2:0] ==3)
+                 r.rdata = duplicate(data0[31:24]);
+               else if(address[2:0] ==4)
+                               r.rdata = duplicate(data0[39:32]);
+               else if(address[2:0] ==5)
+                               r.rdata = duplicate(data0[47:40]);
+               else if(address[2:0] ==6)
+                               r.rdata = duplicate(data0[55:48]);
+               else if(address[2:0] ==7)
+                               r.rdata = duplicate(data0[63:56]);
+      end
+      s_xactor.i_rd_data.enq(r);
+               address=burst_address_generator(rg_read_packet.arlen, rg_read_packet.arsize, rg_read_packet.arburst,rg_read_packet.araddr);
+               Bit#(13) index_address=(address-`BootRomBase)[15:3];
+               if(rg_readburst_counter==rg_read_packet.arlen)begin
+                       rg_readburst_counter<=0;
+                       rd_state<=Idle;
+               end
+               else begin
+                       dmemLSB.put(False,index_address,?);
+                       dmemMSB.put(False,index_address,?);
+                       rg_readburst_counter<=rg_readburst_counter+1;
+               end
+               rg_read_packet.araddr<=address;
+               Bit#(64) new_data=r.rdata;
+               `ifdef verbose $display($time,"\tBootROM : Responding Read Request with CurrAddr: %h Data: %8h BurstCounter: %d BurstValue: %d NextAddress: %h",rg_read_packet.araddr,new_data,rg_readburst_counter,rg_read_packet.arlen,address);  `endif
+   endrule
+
+   interface axi_slave= s_xactor.axi_side;
+endmodule
+endpackage
diff --git a/src/peripherals/clint/clint.bsv b/src/peripherals/clint/clint.bsv
new file mode 100644 (file)
index 0000000..cdd4f4f
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+Copyright (c) 2013, IIT Madras
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+*  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+*  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+*  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+
+package clint;
+       /*=== library imports === */ 
+       import ConfigReg::*;
+       import Semi_FIFOF::*;
+       import AXI4_Lite_Types::*;
+       import BUtils ::*;
+       /*======================== */
+       /*==== Project imports ====*/
+       import defined_types::*;
+       `include "defined_parameters.bsv"       
+       /*=========================*/
+
+       interface Ifc_clint;
+               method Bit#(1) msip_int;
+               method Bit#(1) mtip_int;
+               method Bit#(`Reg_width) mtime;
+               interface AXI4_Lite_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave;
+       endinterface
+       
+       function Reg#(t) writeSideEffect(Reg#(t) r, Action a);
+               return (interface Reg;
+         method t _read = r._read;
+         method Action _write(t x);
+                               r._write(x);
+            a;
+         endmethod
+      endinterface);
+       endfunction
+
+       (*synthesize*)
+       module mkclint(Ifc_clint);
+
+               AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
+               Wire#(Bool) wr_mtimecmp_written<-mkDWire(False);
+               Reg#(Bit#(1)) msip <-mkReg(0);
+               Reg#(Bit#(1)) mtip <-mkReg(0);
+               Reg#(Bit#(64)) rgmtime<-mkReg(0);
+               Reg#(Bit#(64)) rgmtimecmp<-mkReg(0);
+               Reg#(Bit#(64)) csr_mtimecmp=writeSideEffect(rgmtimecmp,wr_mtimecmp_written._write(True));
+               Reg#(Bit#(2)) rg_tick <-mkReg(0);
+
+               rule generate_time_interrupt(!wr_mtimecmp_written);
+                       mtip<=pack(rgmtime>=rgmtimecmp);
+               endrule
+               rule clear_interrupt(wr_mtimecmp_written);
+                       mtip<=0;
+               endrule
+               rule increment_timer;
+                       if(rg_tick==0)begin
+                               rgmtime<=rgmtime+1;
+                       end
+                       rg_tick<=rg_tick+1;
+               endrule
+
+
+               rule axi_read_transaction;
+                       let ar <- pop_o(s_xactor.o_rd_addr);
+                       let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
+                       case (ar.araddr[15:0]) matches
+                               'h0000:         r.rdata=zeroExtend(msip); // MSIP interrupt bit
+                               'h4000:         r.rdata=csr_mtimecmp;
+                               'hbff8:         r.rdata=rgmtime;
+                               default:        begin   r.rdata=0; r.rresp=AXI4_LITE_SLVERR; end
+                       endcase
+                       s_xactor.i_rd_data.enq(r);
+               endrule
+               
+               rule axi_write_transaction;
+                       let aw <- pop_o(s_xactor.o_wr_addr);
+                       let w <- pop_o(s_xactor.o_wr_data);
+                       let r = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_OKAY, buser: 0 };
+
+                       case (aw.awaddr[15:0]) matches
+                               'h0000:         msip<=w.wdata[0]; // MSIP interrupt bit
+                               'h4000:         csr_mtimecmp<=w.wdata;
+                               default:                r.bresp=AXI4_LITE_SLVERR;
+                       endcase
+                       s_xactor.i_wr_resp.enq (r);
+               endrule
+
+               interface axi4_slave = s_xactor.axi_side;
+               method Bit#(1) msip_int=msip;
+               method Bit#(1) mtip_int=mtip;
+               method Bit#(`Reg_width) mtime = rgmtime;
+
+       endmodule
+endpackage
diff --git a/src/peripherals/flexbus/FlexBus_Types.bsv b/src/peripherals/flexbus/FlexBus_Types.bsv
new file mode 100644 (file)
index 0000000..9211640
--- /dev/null
@@ -0,0 +1,1239 @@
+// Copyright (c) 2017 Bluespec, Inc.  All Rights Reserved
+
+package FlexBus_Types;
+
+// ================================================================
+// See export list below
+// ================================================================
+// Exports
+
+export
+
+// RTL-level interfaces (signals/buses)
+FlexBus_Slave_IFC (..),
+FlexBus_Master_IFC (..),
+
+
+// Higher-level enums and structs for the FlexBus
+FlexBus_States (..),
+
+FlexBus_Payload (..),
+FlexBus_Attr (..),
+FlexBus_din (..),
+FlexBus_Signals (..),
+
+// Higher-level FIFO-like interfaces for the 5 AXI4 channels,
+FlexBus_Register_IFC (..),
+FlexBus_Register_Output_IFC (..),
+FlexBus_Register_Input_IFC (..),
+
+AXI4_Slave_to_FlexBus_Master_Xactor_IFC (..),
+
+// Transactors from RTL-level interfacecs to FIFO-like interfaces.
+mkAXI4_Slave_to_FlexBus_Master_Xactor;
+
+// ================================================================
+// BSV library imports
+
+import Vector      :: *;
+import FIFOF       :: *;
+import SpecialFIFOs:: *;
+import Connectable :: *;
+import ConfigReg :: *;
+`include "defined_parameters.bsv"
+
+// ----------------
+// BSV additional libs
+
+import Semi_FIFOF :: *;
+import AXI4_Types   :: *;
+
+import Memory_AXI4 :: *;
+
+// ****************************************************************
+// ****************************************************************
+// Section: RTL-level interfaces
+// ****************************************************************
+// ****************************************************************
+
+// ================================================================
+// These are the signal-level interfaces for an FlexBus master.
+// The (*..*) attributes ensure that when bsc compiles this to Verilog,
+// we get exactly the signals specified in the FlexBus spec.
+
+interface FlexBus_Master_IFC;
+   // FlexBus External Signals
+  
+   // AD inout bus separate for now in BSV
+   (* always_ready, result="AD"       *)  method Bit #(32)   m_AD;                                // out
+
+   //(* always_ready, always_enabled    *)  method Action m_din ((* port="din" *) Bit #(32) din);   // in
+   method Action m_din ((* port="din" *) Bit #(32) din);   // in
+
+   (* always_ready, result="R_Wn"     *)  method Bit #(1)       m_R_Wn;                                   // out
+   (* always_ready, result="TSIZ"     *)  method Bit #(2)       m_TSIZ;                                   // out
+
+   (* always_ready, result="FBCSn"    *)  method Bit #(6)       m_FBCSn;                                  // out
+   (* always_ready, result="BEn_BWEn" *)  method Bit #(4)       m_BE_BWEn;                                // out
+   (* always_ready, result="TBSTn"    *)  method Bit #(1)       m_TBSTn;                                  // out
+   (* always_ready, result="OEn"      *)  method Bit #(1)       m_OEn;                                    // out
+
+   (* always_ready, result="ALE"      *)  method Bit #(1)       m_ALE;                                    // out
+   //(* always_ready, always_enabled    *)  method Action m_TAn ((* port="TAn" *) Bit #(1) tAn);            // in
+   method Action m_TAn ((* port="TAn" *) Bit #(1) tAn);            // in
+
+endinterface: FlexBus_Master_IFC
+
+interface FlexBus_Register_Input_IFC;
+       method Action reset (Bit#(32) ad_bus);
+        method Action m_ad_bus (Bit#(32) ad_bus);
+        method Action m_data_bus (Bit#(32) data_bus);
+endinterface: FlexBus_Register_Input_IFC
+
+interface FlexBus_Register_Output_IFC;
+       (* always_ready, always_enabled *)   method Bit#(6) m_FBCSn(); 
+       (* always_ready, always_enabled *)   method Bit#(6) m_SWS(); 
+        (* always_ready, always_enabled *)   method Bit#(1) m_SWS_EN(); 
+       (* always_ready, always_enabled *)   method Bit#(2) m_ASET(); 
+       (* always_ready, always_enabled *)   method Bit#(2) m_RDAH(); 
+       (* always_ready, always_enabled *)   method Bit#(2) m_WRAH(); 
+       (* always_ready, always_enabled *)   method Bit#(6) m_WS(); 
+       (* always_ready, always_enabled *)   method Bit#(1) m_AA(); 
+       (* always_ready, always_enabled *)   method Bit#(2) m_PS(); 
+       (* always_ready, always_enabled *)   method Bit#(1) m_BEM(); 
+       (* always_ready, always_enabled *)   method Bit#(1) m_BSTR(); 
+       (* always_ready, always_enabled *)   method Bit#(1) m_BSTW();
+endinterface: FlexBus_Register_Output_IFC
+
+interface FlexBus_Register_IFC;
+       interface FlexBus_Register_Input_IFC inp_side;
+       interface FlexBus_Register_Output_IFC op_side;
+endinterface: FlexBus_Register_IFC
+
+// ================================================================
+// These are the signal-level interfaces for an AXI4-Lite slave.
+// The (*..*) attributes ensure that when bsc compiles this to Verilog,
+// we get exactly the signals specified in the ARM spec.
+
+interface FlexBus_Slave_IFC ;
+  
+   (* always_ready, always_enabled    *) method Action m_AD            ( (* port="AD"       *)  Bit #(32)   i_AD);                         // in
+
+
+   (* always_ready, always_enabled    *) method Action m_ALE           ( (* port="ALE"      *)  Bit #(1)         i_ALE);                           // in
+                                                                               
+   (* always_ready, always_enabled    *) method Action m_R_Wn          ( (* port="R_Wn"     *)  Bit #(1)         i_R_Wn);                          // in
+   (* always_ready, always_enabled    *) method Action m_TSIZ          ( (* port="TSIZ"     *)  Bit #(2)         i_TSIZ);                          // in
+                                                                               
+   (* always_ready, always_enabled    *) method Action m_FBCSn                 ( (* port="FBCSn"    *)  Bit #(6)         i_FBCSn);                         // in
+   (* always_ready, always_enabled    *) method Action m_BE_BWEn       ( (* port="BE_BWEn"  *)  Bit #(4)         i_BE_BWEn);                       // in
+   (* always_ready, always_enabled    *) method Action m_TBSTn                 ( (* port="TBSTn"    *)  Bit #(1)         i_TBSTn);                         // in
+   (* always_ready, always_enabled    *) method Action m_OEn           ( (* port="OEn"      *)  Bit #(1)         i_OEn);                           // in
+                                                                               
+   (* always_ready, result="din"   *)  method Bit #(32) m_din;                                                // out
+   (* always_ready, result="TAn"   *)  method Bit #(1) m_TAn;                                                      // out
+
+endinterface: FlexBus_Slave_IFC
+
+
+// ================================================================
+// Connecting signal-level interfaces
+
+instance Connectable #(FlexBus_Master_IFC ,
+                      FlexBus_Slave_IFC  );
+
+   module mkConnection #(FlexBus_Master_IFC  flexbus_m,
+                        FlexBus_Slave_IFC  flexbus_s)
+                      (Empty);
+
+    (* fire_when_enabled, no_implicit_conditions *)
+    rule rl_flexbus_AD_signals;
+        flexbus_s.m_AD      (flexbus_m.m_AD);
+    endrule
+
+
+      (* fire_when_enabled, no_implicit_conditions *)
+      rule rl_flexbus_Attr_signals;
+        flexbus_s.m_ALE     (flexbus_m.m_ALE);
+        flexbus_s.m_R_Wn    (flexbus_m.m_R_Wn);
+        flexbus_s.m_TSIZ    (flexbus_m.m_TSIZ);
+      endrule
+      (* fire_when_enabled, no_implicit_conditions *)
+      rule rl_flexbus_signals;
+        flexbus_s.m_FBCSn   (flexbus_m.m_FBCSn);
+        flexbus_s.m_BE_BWEn (flexbus_m.m_BE_BWEn);
+        flexbus_s.m_TBSTn   (flexbus_m.m_TBSTn);
+        flexbus_s.m_OEn     (flexbus_m.m_OEn);
+      endrule
+      (* fire_when_enabled *)
+      //(* fire_when_enabled, no_implicit_conditions *)
+      rule rl_flexbus_input_signals;
+        flexbus_m.m_din (flexbus_s.m_din);
+        flexbus_m.m_TAn (flexbus_s.m_TAn);
+      endrule
+
+   endmodule
+endinstance
+
+// ****************************************************************
+// ****************************************************************
+// Section: Higher-level FIFO-like interfaces and transactors
+// ****************************************************************
+// ****************************************************************
+
+// ================================================================
+// Higher-level types for payloads (rather than just bits)
+
+typedef enum { IDLE, FlexBus_S0_DEQ_WR_FIFOS, FlexBus_S0_DEQ_RD_FIFOS, FlexBus_S1_ADDR, FlexBus_S2_WRITE, FlexBus_S3_BURST, FlexBus_S4_HOLD } FlexBus_States deriving (Bits, Eq, FShow);
+typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS, FlexBus_WRITE_DUMMY1, FlexBus_WRITE_DUMMY2 } FlexBus_States_wr deriving (Bits, Eq, FShow);
+typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS} FlexBus_States_rd deriving (Bits, Eq, FShow);
+
+//FlexBus Addr. Data Payload
+
+typedef struct {
+   Bit #(32)     s_AD;                                     // out
+   } FlexBus_Payload
+deriving (Bits, FShow);
+
+typedef struct {
+   Bit #(32)    din;                                    // in
+   } FlexBus_din 
+deriving (Bits, FShow);
+
+//FlexBus Attributes
+
+typedef struct {
+   Bit #(1)         s_R_Wn;                                   // out
+   Bit #(2)         s_TSIZ;                                   // out
+   } FlexBus_Attr 
+deriving (Bits, FShow);
+
+typedef struct {
+   Bit #(6)         s_FBCSn;                                  // out
+   Bit #(4)         s_BEn_BWEn;                               // out
+   Bit #(1)         s_TBSTn;                                  // out
+   Bit #(1)         s_OEn;                                    // out
+   } FlexBus_Signals #(numeric type wd_addr, numeric type wd_data)
+deriving (Bits, FShow);
+
+// FlexBus Control Signals
+
+// Bit              s_ALE;                                    // out
+// Bit              s_TAn;                                    // in
+
+/* ----------------------------------------------------------------
+
+   module mkFlexBusTop (Empty);
+       AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
+                                                  flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
+
+   endmodule
+
+
+// ---------------------------------------------------------------- */
+// AXI4 Lite Slave to FlexBus Master transactor interface
+
+interface AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(numeric type wd_addr,
+                                      numeric type wd_data,
+                                      numeric type wd_user);
+   method Action reset;
+
+   // AXI side
+   interface AXI4_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side;
+
+   // FlexBus side
+   interface FlexBus_Master_IFC flexbus_side;
+
+endinterface: AXI4_Slave_to_FlexBus_Master_Xactor_IFC
+
+// ----------------------------------------------------------------
+
+// AXI4 Lite Slave to FlexBus Master transactor 
+
+module mkAXI4_Slave_to_FlexBus_Master_Xactor 
+               (AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(wd_addr, wd_data, wd_user))
+   provisos (Add#(a__, 8, wd_addr),
+        Add#(b__, 64, wd_data),
+            //Bits#(Bit#(56), wd_addr),
+            //Bits#(Bit#(64), wd_data),
+            //Bits#(Bit#(32), wd_fb_addr),
+            //Bits#(Bit#(32), wd_fb_data),
+            //Bits#(Inout#(Bit#(32)), a__),
+           // Bits#(Inout#(Bit#(32)), wd_Fb_addr),
+            //Bits#(Inout#(Bit#(32)), 48),
+             Div#(wd_data, 16, 4));
+   Bool unguarded = True;
+   Bool guarded   = False;
+   //let wD_FB_ADDR = valueOf(wd_fb_addr);
+   //let wD_FB_DATA = valueOf(wd_fb_data);
+
+   FlexBus_Register_IFC register_ifc <- mkFlexBus_Registers;
+
+   Reg#(Bit#(32))       r_AD           <- mkReg(0); 
+   Reg#(Bit#(32))       r_din          <- mkReg(0); 
+   Reg#(Bit#(1))       r_R_Wn          <- mkReg(1'b1); 
+   Reg#(Bit#(2))       r_TSIZ          <- mkReg(2'b00);  
+   Reg#(Bit#(6))       r_FBCSn         <- mkReg(6'h3F);  
+   Reg#(Bit#(4))       r_BE_BWEn       <- mkReg(4'hF);
+   Reg#(Bit#(1))       r_TBSTn         <- mkReg(1'b1);   
+   Reg#(Bit#(1))       r_OEn           <- mkReg(1'b1);      
+   Reg#(Bit#(1))       r_ALE           <- mkReg(1'b0);       
+   Reg#(Bit#(1))           r_ext_TAn   <- mkReg(1'b0);         
+   Reg#(Bit#(1))           r_int_TAn   <- mkReg(1'b1);         
+
+   Reg#(Bit#(2))       r_ASET          <- mkReg(2'b00);  
+   Reg#(Bit#(2))       r_PS            <- mkReg(2'b00);  
+   Reg#(Bit#(3))       r_rpt_cnt       <- mkReg(3'b000);  
+   Reg#(Bit#(2))       r_burst_cnt     <- mkReg(2'b00);  
+   Reg#(Bit#(2))       r_hld_cnt       <- mkReg(2'b00);  
+   Reg#(Bit#(6))       r_WS_cnt        <- mkReg(6'h00);  
+   Reg#(Bit#(6))       r_SWS_cnt       <- mkReg(6'h00);  
+   Reg#(Bit#(wd_addr))  r_awaddr    <- mkReg(0);
+   Reg#(Bit#(2))       r_awsize    <- mkReg(0);
+   Reg#(Bit#(wd_addr))  r2_awaddr   <- mkReg(0);
+   Reg#(Bit#(wd_data))  r_wdata     <- mkReg(0);
+   Reg#(AXI4_Resp)      r_wrbresp      <- mkReg(AXI4_OKAY);  
+   Reg#(AXI4_Resp)      r_rresp            <- mkReg(AXI4_OKAY);  
+   Reg#(Bit#(wd_data))  r_rd_data        <- mkReg(0);
+   Reg#(Bit#(TDiv#(wd_data,8))) r1_wstrb <- mkReg(0);
+   Reg#(Bit#(TDiv#(wd_data,8))) r2_wstrb <- mkReg(0);
+   Reg#(Bit#(wd_addr))  r_araddr         <- mkReg(0);
+   Reg#(Bit#(wd_addr))  r2_araddr        <- mkReg(0);
+   Reg#(Bit#(2))       r_arsize         <- mkReg(0);
+   Reg#(Bit#(4))       r_arid           <- mkReg(0);
+   Reg#(Bit#(4))       r_awid           <- mkReg(0);
+   Reg#(Bit#(1))       wr_pending       <- mkReg(0);
+   Reg#(Bit#(1))       r_chk_fifos_wr   <- mkReg(0);
+   Reg#(Bit#(1))       r_chk_fifos_rd   <- mkReg(0);
+   ConfigReg#(Bit#(1))         rd_wrb      <- mkConfigReg(1);
+   Reg#(Bool)          r_rready        <- mkReg(False);       
+   Reg#(Bool)          r2_rready       <- mkReg(False);       
+
+   Reg#(Bool)          r1_awvalid      <- mkReg(False);       
+   Reg#(Bool)          r2_awvalid      <- mkReg(False);       
+   Reg#(Bool)          r1_wvalid       <- mkReg(False);       
+   Reg#(Bool)          r2_wvalid       <- mkReg(False);       
+   Reg#(Bool)              r1_arvalid  <- mkReg(False);       
+   Reg#(Bool)          r2_arvalid      <- mkReg(False);       
+
+   Reg#(Bool)          r1_OEn          <- mkReg(True);       
+
+   Reg#(Bit#(8))  r_AD_32bit_data_byte1  <- mkReg(0);
+   Reg#(Bit#(8))  r_AD_32bit_data_byte2  <- mkReg(0);
+   Reg#(Bit#(8))  r_AD_32bit_data_byte3  <- mkReg(0);
+   Reg#(Bit#(8))  r_AD_32bit_data_byte4  <- mkReg(0);
+
+   Reg#(Bit#(8))  r_AD_32bit_addr_byte1  <- mkReg(0);
+   Reg#(Bit#(8))  r_AD_32bit_addr_byte2  <- mkReg(0);
+   Reg#(Bit#(8))  r_AD_32bit_addr_byte3  <- mkReg(0);
+   Reg#(Bit#(8))  r_AD_32bit_addr_byte4  <- mkReg(0);
+
+   Reg#(Bit#(8))  r_rd_data_32bit_byte1  <- mkReg(0);
+   Reg#(Bit#(8))  r_rd_data_32bit_byte2  <- mkReg(0);
+   Reg#(Bit#(8))  r_rd_data_32bit_byte3  <- mkReg(0);
+   Reg#(Bit#(8))  r_rd_data_32bit_byte4  <- mkReg(0);
+
+   Reg#(Bit#(32))  r_MBAR  <- mkReg(32'h04000000);
+
+   Reg#(FlexBus_States) flexbus_state <- mkReg(IDLE);
+   Reg#(FlexBus_States_rd) flexbus_state_rd <- mkReg(FlexBus_S0_CHK_FIFOS);
+   Reg#(FlexBus_States_wr) flexbus_state_wr <- mkReg(FlexBus_S0_CHK_FIFOS);
+
+   // These FIFOs are guarded on BSV side, unguarded on AXI side
+   FIFOF #(AXI4_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded);
+   FIFOF #(AXI4_Wr_Data #(wd_data))          f_wr_data <- mkGFIFOF (unguarded, unguarded);
+   FIFOF #(AXI4_Wr_Resp #(wd_user))          f_wr_resp <- mkGFIFOF (guarded, unguarded);
+
+   FIFOF #(AXI4_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded);
+   FIFOF #(AXI4_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded);
+
+   Reg#(Maybe#(Bit#(1)))  c_TAn[2] <- mkCReg(2, tagged Invalid);
+   Reg#(Maybe#(Bit#(32))) c_din[2] <- mkCReg(2, tagged Invalid);
+
+   //TriState#(Bit#(32)) tri_AD_out <- mkTriState(r1_OEn,r_AD);
+
+   // ----------------------------------------------------------------
+
+   rule rl_OEn;
+       if (r_OEn == 1'b0)
+               r1_OEn <= False;
+        else
+               r1_OEn <= True;
+   endrule
+
+   rule rl_state_S0_CHK_FIFO_RD(flexbus_state_rd == FlexBus_S0_CHK_FIFOS);
+       `ifdef verbose_debug $display("STATE S0 CHK FIFOS RD FIRED"); `endif
+        if (f_rd_addr.notEmpty) begin
+                   register_ifc.inp_side.m_ad_bus(f_rd_addr.first.araddr[31:0]);
+            flexbus_state_rd <= FlexBus_S0_DEQ_FIFOS;
+            `ifdef verbose_debug_l2 $display("READ ADDR FIFO WAS READ FIRST  r_araddr=%h \n", f_rd_addr.first.araddr); `endif
+        end
+   endrule
+
+  (* preempts = "rl_check_read_fifo, rl_check_write_fifo" *) 
+   rule rl_check_read_fifo (r_chk_fifos_rd == 1'b1 && f_rd_addr.notEmpty); 
+                rd_wrb <= 1'b1;
+                r_chk_fifos_rd <= 1'b0;
+                r_chk_fifos_wr <= 1'b0;
+   endrule
+
+   rule rl_check_write_fifo(r_chk_fifos_wr == 1'b1 && f_wr_addr.notEmpty && f_wr_data.notEmpty);
+                   if (f_wr_addr.first.awaddr[31:16] != r_MBAR[31:16]) begin
+                    rd_wrb <= 1'b0;
+                    r_chk_fifos_rd <= 1'b0;
+                    r_chk_fifos_wr <= 1'b0;
+            end
+   endrule
+
+   rule rl_state_S0_CHK_FIFOS_WR(flexbus_state_wr == FlexBus_S0_CHK_FIFOS);
+       `ifdef verbose_debug $display("STATE S0 CHK FIFOS WR FIRED"); `endif
+        if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
+                   if (f_wr_addr.first.awaddr[31:16] == r_MBAR[31:16]) begin
+                           f_wr_addr.deq; f_wr_data.deq;
+                   end
+                   else begin
+                flexbus_state_wr <= FlexBus_S0_DEQ_FIFOS;
+                   end
+                   register_ifc.inp_side.m_ad_bus(f_wr_addr.first.awaddr[31:0]);
+                   register_ifc.inp_side.m_data_bus(f_wr_data.first.wdata[31:0]);
+        end
+   endrule
+
+   rule rl_state_S0_DEQ_FIFOS (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS || flexbus_state_wr == FlexBus_S0_DEQ_FIFOS);
+       `ifdef verbose_debug $display("STATE S0 DEQ FIFOS FIRED"); `endif
+        if (rd_wrb == 1'b1) begin
+                flexbus_state <= FlexBus_S0_DEQ_RD_FIFOS;
+                flexbus_state_rd <= IDLE;
+                flexbus_state_wr <= IDLE;
+        end
+        else if (rd_wrb == 1'b0) begin
+                flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
+                flexbus_state_rd <= IDLE;
+                flexbus_state_wr <= IDLE;
+        end
+        if (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS && flexbus_state_wr == FlexBus_S0_DEQ_FIFOS) wr_pending <= 1'b1;
+   endrule
+
+   rule rl_state_S0_DEQ_WR_FIFOS (flexbus_state == FlexBus_S0_DEQ_WR_FIFOS);
+       `ifdef verbose_debug $display("STATE S0 DEQ WR FIFOS FIRED"); `endif
+       r_ASET <= register_ifc.op_side.m_ASET;
+       Bit#(3) v_awsize = 3'b000;
+       if ((f_wr_addr.notEmpty) )  begin
+               r1_awvalid <= f_wr_addr.notEmpty;
+               f_wr_addr.deq;
+        r_chk_fifos_wr <= 1'b1;
+        r_chk_fifos_rd <= 1'b1;
+               AXI4_Wr_Addr#(wd_addr, wd_user) wr_addr = f_wr_addr.first;
+               r_awaddr <= f_wr_addr.first.awaddr;
+               v_awsize = f_wr_addr.first.awsize;
+            r_awid <= f_wr_addr.first.awid;
+                case (v_awsize) matches
+                       {3'b000}: r_awsize <= 2'b01;
+                       {3'b001}: r_awsize <= 2'b10;
+                       {3'b010}: r_awsize <= 2'b00;
+               endcase
+                `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_awaddr=%h \n", r_awaddr); `endif
+        end
+       if ((f_wr_data.notEmpty) ) begin
+               r1_wvalid <= f_wr_data.notEmpty;
+               f_wr_data.deq;
+                `ifdef verbose_debug_l2 $display("DATA FIFO WAS NOT EMPTY SO I DEQUEUED\n"); `endif
+               AXI4_Wr_Data#(wd_data) wr_data = f_wr_data.first;
+               r_wdata <= f_wr_data.first.wdata;
+               r1_wstrb <= f_wr_data.first.wstrb;
+               `ifdef verbose_debug_l2 $display(" dequeued first r_wdata = %h", r_wdata); `endif
+        end
+        if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
+                flexbus_state <= FlexBus_S1_ADDR;
+        end
+   endrule
+
+   rule rl_S0_DEQ_RD_FIFOS (flexbus_state == FlexBus_S0_DEQ_RD_FIFOS);
+       `ifdef verbose_debug $display("STATE S0 DEQ RD FIFOS FIRED"); `endif
+       r_ASET <= register_ifc.op_side.m_ASET;
+       Bit#(3) v_arsize = 3'b000;
+       if ((f_rd_addr.notEmpty) ) begin
+               r1_arvalid <= f_rd_addr.notEmpty;
+               f_rd_addr.deq;
+        r_chk_fifos_wr <= 1'b1;
+        r_chk_fifos_rd <= 1'b1;
+               AXI4_Rd_Addr#(wd_addr, wd_user) rd_addr = f_rd_addr.first;
+               r_araddr <= f_rd_addr.first.araddr;
+               v_arsize = f_rd_addr.first.arsize;
+            r_arid <= f_rd_addr.first.arid;
+                case (v_arsize) matches
+                       {3'b000}: r_arsize <= 2'b01;
+                       {3'b001}: r_arsize <= 2'b10;
+                       {3'b010}: r_arsize <= 2'b00;
+               endcase
+               r_rd_data_32bit_byte1 <= 0;
+               r_rd_data_32bit_byte2 <= 0;
+               r_rd_data_32bit_byte3 <= 0;
+               r_rd_data_32bit_byte4 <= 0;
+                `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_araddr=%h \n", f_rd_addr.first.araddr); `endif
+        end
+        if (f_rd_addr.notEmpty) begin
+                flexbus_state <= FlexBus_S1_ADDR;
+        end
+   endrule
+
+   rule rl_enq_wr_resp;
+   Bool bready = f_wr_resp.notFull; 
+   if (f_wr_resp.notFull) 
+       f_wr_resp.enq (AXI4_Wr_Resp {bresp:r_wrbresp,
+                                         buser:0,
+                                         bid:r_awid});
+   endrule
+
+
+   rule rl_enq_rd_data;
+       Bool rready = f_rd_data.notFull; 
+       if (f_rd_data.notFull && r2_rready) begin 
+               f_rd_data.enq (AXI4_Rd_Data {rdata: r_rd_data,
+                                                 rresp: r_rresp,
+                                                 rlast: True,
+                                                 ruser:0,
+                          rid:r_arid});
+               //AXI4_Slave_IFC.m_rready(True);
+               `ifdef verbose_debug $display("RD DATA FIFO WAS NOT FULL SO I ENQUEUED r_rd_data=%h r2_rready= %b\n", r_rd_data, r2_rready); `endif
+       end
+   endrule
+
+   rule rl_state_S1_ADDR (flexbus_state == FlexBus_S1_ADDR); //Address state
+       `ifdef verbose_debug $display("STATE S1 FIRED");`endif
+        r_PS   <= register_ifc.op_side.m_PS;  
+       r_WS_cnt <= register_ifc.op_side.m_WS;
+       r_OEn <= 1'b1;
+       r_BE_BWEn <= 4'hF;
+       r_FBCSn <= 6'h3F;
+        r_ALE <= 1'b1;
+        `ifdef verbose_debug_l2 $display(" r_ASET was ASSIGNED = %b", r_ASET); `endif
+               if (r_rpt_cnt == 3'b000) begin
+                       if (r1_arvalid) begin
+                               r_AD <= r_araddr[31:0];
+                               r_R_Wn <= 1'b1;   // Read
+                               r_TSIZ <= r_arsize; 
+                       end
+                       else if (r1_awvalid && r1_wvalid) begin
+                               r_AD <= r_awaddr[31:0];
+                               r_R_Wn <= 1'b0;   // WriteBar
+                               r_TSIZ <= r_awsize; 
+                       end
+               end
+               else begin
+                       if (r_R_Wn == 1'b0) r_AD <= r_awaddr[31:0];
+                       else r_AD <= r_araddr[31:0];
+                       r_TBSTn <= 1'b1;
+                       r_TSIZ <= register_ifc.op_side.m_PS;
+               end
+        if (( r_ASET != 2'b00) ) begin 
+               r_ASET <= r_ASET - 1; 
+       end
+       else begin 
+               flexbus_state <= FlexBus_S2_WRITE;
+               if (r_rpt_cnt != 3'b000) 
+                       r_rpt_cnt <= r_rpt_cnt -1;
+       end
+   endrule
+
+   rule rl_assign_AD_bus_reg (flexbus_state == FlexBus_S1_ADDR) ; // Address an Attributes Phase
+       `ifdef verbose_debug_l2 $display(" ASSIGN AD BUS FIRED"); `endif
+
+        r2_awvalid <= r1_awvalid;
+        r2_wvalid  <= r1_wvalid;
+        r2_wstrb   <= r1_wstrb;
+        r2_arvalid <= r1_arvalid;
+
+        r2_araddr <= r_araddr;
+        r2_awaddr <= r_awaddr;
+
+       r_AD_32bit_data_byte1   <= pack(r_wdata[7:0]); 
+       r_AD_32bit_data_byte2   <= pack(r_wdata[15:8]); 
+       r_AD_32bit_data_byte3 <= pack(r_wdata[23:16]); 
+       r_AD_32bit_data_byte4 <= pack(r_wdata[31:24]);
+       r_AD_32bit_addr_byte1  <= pack(r_awaddr[31:24]); 
+       r_AD_32bit_addr_byte2  <= pack(r_awaddr[23:16]); 
+       r_AD_32bit_addr_byte3  <= pack(r_awaddr[15:8]); 
+       r_AD_32bit_addr_byte4  <= pack(r_awaddr[7:0]); 
+        `ifdef verbose_debug_l2 $display("r_wdata after ASSIGN = %h r_PS = %b r_AD_32bit_data_byte1=%h ", r_wdata, r_PS, r_AD_32bit_data_byte1);
+        $display("r_awaddr after ASSIGN = %h r_PS = %b r_AD_32bit_addr_byte1=%h ", r_awaddr, r_PS, r_AD_32bit_addr_byte1); `endif
+   endrule
+
+   rule rl_assign_rd_data;
+       r_rd_data[63:0] <= pack({32'h00000000, r_rd_data_32bit_byte4, r_rd_data_32bit_byte3, r_rd_data_32bit_byte2, r_rd_data_32bit_byte1});
+        r2_rready <= r_rready;
+        `ifdef verbose_debug_l2 $display("ASSIGN READ DATA FIRED AND r_rd_data = %h r_rready=%b r2_rready=%b", r_rd_data, r_rready, r2_rready);`endif
+   endrule
+  
+   rule rl_read_ext_signals;
+       if (isValid(c_TAn[1])) begin
+               r_ext_TAn <= fromMaybe(?,c_TAn[1]);
+               c_TAn[1]<= tagged Invalid;
+       end
+       if (isValid(c_din[1])) begin
+               r_din <= fromMaybe(?,c_din[1]);
+               c_din[1]<= tagged Invalid;
+       end
+    //r_din <= tri_AD_out._read;
+   endrule
+
+   rule rl_state_S2_WRITE (flexbus_state == FlexBus_S2_WRITE); //Write Phase
+       `ifdef verbose_debug $display("STATE S2 FIRED"); `endif
+       r_ALE <= 1'b0;
+        r_FBCSn <= register_ifc.op_side.m_FBCSn;
+       r_SWS_cnt <= register_ifc.op_side.m_SWS;
+        if (r_R_Wn == 1'b1)
+               r_hld_cnt <= register_ifc.op_side.m_RDAH;
+       else 
+               r_hld_cnt <= register_ifc.op_side.m_WRAH;
+                  if (r_R_Wn == 1'b1) begin
+                       r_OEn <= 1'b0;
+                       if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
+                               r_TBSTn <= 1'b0; 
+                       end
+                  end
+                   else begin
+                       // ASSIGN WRITE DATA DEPENDING ON BURST INHIBITED OR NOT
+                       if ((r_rpt_cnt == 3'b000) ) begin 
+                               if (r_PS == 2'b01) begin
+                                       r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                               end
+                               else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
+                                       r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                               end
+                               else begin
+                                       r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
+                               end
+                       end
+                        else if (r_rpt_cnt == 3'b011) begin 
+                                       r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                       end
+                       else if (r_rpt_cnt == 3'b010)
+                                       r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                        else if  (r_rpt_cnt == 3'b001) begin
+                               if (r_awsize == 2'b00) begin
+                                       if ((r_PS == 2'b10) || (r_PS == 2'b11))
+                                               r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                                       else if ((r_PS == 2'b01))
+                                               r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                                       end
+                               else if (r_awsize == 2'b10) begin
+                                       if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                                       
+                               end
+                       end
+                       if (register_ifc.op_side.m_BEM == 1'b1) 
+                               r_BE_BWEn <= r2_wstrb[3:0];
+                       if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
+                               r_TBSTn <= 1'b0; 
+                       end
+                  end
+                if (r_WS_cnt == 6'h00) begin
+                   if (r_ext_TAn == 1'b0) begin
+                       //r_int_TAn <= 1'b0;
+                       flexbus_state <= FlexBus_S3_BURST;
+                   end
+                   if (register_ifc.op_side.m_AA == 1'b1) begin
+                       r_int_TAn <= 1'b1;
+                    end
+                   r_WS_cnt <= register_ifc.op_side.m_WS;
+                   if (r_R_Wn == 1'b1) begin
+                       if (r_arsize == 2'b00) begin
+                               if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
+                                       if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
+                                       if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
+                               end
+                               else if ((register_ifc.op_side.m_BSTR == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
+                                       if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
+                                       if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
+                               end
+                       end
+                       else if (r_arsize == 2'b10) begin
+                               if ((register_ifc.op_side.m_BSTR == 1'b1) && (r_PS == 2'b01)) begin
+                                       r_burst_cnt <= 2'b01;
+                               end 
+                               else if ((register_ifc.op_side.m_BSTR == 1'b0) && (r_PS == 2'b01)) begin
+                                       if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
+                               end
+                       end 
+                  end
+                   else begin
+                       if (r_awsize == 2'b00) begin
+                               if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
+                                       if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
+                                       if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
+                               end
+                               else if ((register_ifc.op_side.m_BSTW == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
+                                       if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
+                                       if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
+                               end
+                       end
+                       else if (r_awsize == 2'b10) begin
+                               if ((register_ifc.op_side.m_BSTW == 1'b1) && (r_PS == 2'b01)) begin
+                                       r_burst_cnt <= 2'b01;
+                               end 
+                               else if ((register_ifc.op_side.m_BSTW == 1'b0) && (r_PS == 2'b01)) begin
+                                       if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
+                               end
+                       end 
+                  end
+                end
+               else begin
+                   r_WS_cnt <= r_WS_cnt -1;
+            end
+             `ifdef verbose_debug_l2 $display("r_AD after WRITE = %h r_ASET=%b r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h ", r_AD, r_ASET, r_R_Wn, r_PS, r_AD_32bit_data_byte1); `endif
+   endrule
+
+   rule rl_state_S3_BURST (flexbus_state == FlexBus_S3_BURST); // Data Phase with/without bursting terminated prematurely externally
+       `ifdef verbose_debug $display("STATE S3 FIRED"); `endif
+       `ifdef verbose_debug_l2
+        $display("r_rpt_cnt in BURST = %b", r_rpt_cnt);
+        $display("r_burst_cnt in BURST = %b, BSTW=%b", r_burst_cnt,register_ifc.op_side.m_BSTW);
+        $display (" r_AD in BURST = %h", r_AD);
+        $display("r_AD after WRITE = %h r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h r_AD_32bit_data_byte2=%h r_AD_32bit_data_byte3=%h", r_AD, r_R_Wn, r_PS, r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3);
+       `endif
+       if (r_ext_TAn == 1'b1) begin // premature external termination SLVERR response
+               flexbus_state <= FlexBus_S4_HOLD;
+               if (r_R_Wn == 1'b1) begin
+               r_rresp <= AXI4_SLVERR; //SLVERR
+        end else begin
+               r_wrbresp <= AXI4_SLVERR; //SLVERR
+        end
+       end
+       else if (r_rpt_cnt == 3'b001) begin
+               if (r_R_Wn == 1'b1) begin
+                       if (r_arsize == 2'b00) begin
+                               if (r_PS == 2'b01) begin
+                                       r_rd_data_32bit_byte4 <= r_din[7:0];
+                               end
+                               else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
+                                       r_rd_data_32bit_byte3 <= r_din[7:0];
+                                       r_rd_data_32bit_byte4 <= r_din[15:8];
+                               end
+                       end
+                       else if (r_arsize == 2'b10) begin
+                               if (r_PS == 2'b01)
+                                       r_rd_data_32bit_byte2 <= r_din[7:0];
+                       end
+                       r_rready <= True;
+                       //r_rpt_cnt <= r_rpt_cnt -1;
+               end
+                //else
+               flexbus_state <= FlexBus_S4_HOLD;
+               if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now 
+                       r_OEn <= 1'b1;
+                       r_BE_BWEn <= 4'hF;
+                       r_FBCSn <= 6'h3F;
+               end
+        end
+       else if (r_rpt_cnt != 3'b000) begin
+               flexbus_state <= FlexBus_S1_ADDR;
+               r_ASET <= register_ifc.op_side.m_ASET;
+               if (register_ifc.op_side.m_AA == 1'b1) begin
+                       r_OEn <= 1'b1;
+                       r_BE_BWEn <= 4'hF;
+                       r_FBCSn <= 6'h3F;
+               end
+               if (r_R_Wn == 1'b1) begin
+                       if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b100))
+                               r_rd_data_32bit_byte1 <= r_din[7:0];
+                       else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b011))
+                               r_rd_data_32bit_byte2 <= r_din[7:0];
+                               else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b010)) begin
+                               if (r_arsize == 2'b00)
+                                       r_rd_data_32bit_byte3 <= r_din[7:0];
+                               else if (r_arsize == 2'b10) 
+                                       r_rd_data_32bit_byte1 <= r_din[7:0];
+                       end
+                       else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
+                               r_rd_data_32bit_byte1 <= r_din[7:0];
+                               r_rd_data_32bit_byte2 <= r_din[15:8];
+                       end
+               end
+        end
+        else if (r_burst_cnt == 2'b01) begin
+               if (r_ext_TAn == 1'b1) begin
+                       flexbus_state <= FlexBus_S4_HOLD;
+               end
+               else begin
+                       if (r_R_Wn == 1'b0) begin
+                               if (r_awsize == 2'b00) begin
+                                               if (r_PS == 2'b01) 
+                                               r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                                               else if ((r_PS == 2'b10) || (r_PS == 2'b11)) 
+                                               r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                                       //else
+                                       //      r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
+                               end
+                               else if (r_awsize == 2'b10) begin
+                                       if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                               end
+                       end
+                       else begin
+                               if (r_arsize == 2'b00) begin
+                                               if (r_PS == 2'b01) 
+                                               r_rd_data_32bit_byte3 <= r_din[7:0];
+                                               else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
+                                               r_rd_data_32bit_byte1 <= r_din[7:0];
+                                               r_rd_data_32bit_byte2 <= r_din[15:8];
+                                       end
+                               end
+                               else if (r_arsize == 2'b10) begin
+                                               if (r_PS == 2'b01) 
+                                               r_rd_data_32bit_byte1 <= r_din[7:0];
+                               end
+                       end
+                       if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
+                               if (r_SWS_cnt == 6'h00) begin 
+                                       r_SWS_cnt <= register_ifc.op_side.m_SWS;
+                                       if (register_ifc.op_side.m_AA == 1'b1) begin
+                                               r_int_TAn <= 1'b1;
+                                               r_OEn <= 1'b1;
+                                               r_BE_BWEn <= 4'hF;
+                                               r_FBCSn <= 6'h3F;
+                                        end
+                                       r_burst_cnt <= r_burst_cnt -1;
+                                       //flexbus_state <= FlexBus_S4_HOLD;
+                               end
+                               else begin
+                                       r_SWS_cnt <= r_SWS_cnt -1;
+                               end
+                        end
+                        else begin
+                               if (r_WS_cnt == 6'h00) begin
+                                       r_WS_cnt <= register_ifc.op_side.m_WS;
+                                       if (register_ifc.op_side.m_AA == 1'b1) begin
+                                               r_int_TAn <= 1'b1;
+                                               r_OEn <= 1'b1;
+                                               r_BE_BWEn <= 4'hF;
+                                               r_FBCSn <= 6'h3F;
+                                       end
+                                       r_burst_cnt <= r_burst_cnt -1;
+                                       //flexbus_state <= FlexBus_S4_HOLD;
+                               end
+                               else
+                                       r_WS_cnt <= r_WS_cnt - 1;
+                       end
+               end
+       end
+       else if (r_burst_cnt != 2'b00) begin
+               if (r_R_Wn == 1'b0) begin
+                               if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11)) 
+                               r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                               else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin 
+                               r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                        end
+                               //else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b01)) 
+                       //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+                               //else if ((r_PS == 2'b10) || (r_PS == 2'b11)) 
+                       //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
+               end
+               else begin
+                               if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11)) 
+                               r_rd_data_32bit_byte1 <= r_din[7:0];
+                               else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin 
+                               r_rd_data_32bit_byte2 <= r_din[7:0];
+                       end
+               end
+               if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
+                       if (r_SWS_cnt == 6'h00) begin 
+                               r_SWS_cnt <= register_ifc.op_side.m_SWS;
+                               if (register_ifc.op_side.m_AA == 1'b1)
+                                       r_int_TAn <= 1'b1;
+                               r_burst_cnt <= r_burst_cnt -1;
+                       end
+                       else begin
+                               r_SWS_cnt <= r_SWS_cnt -1;
+                       end
+                end
+               else begin 
+                       if (r_WS_cnt == 6'h00) begin
+                               r_WS_cnt <= register_ifc.op_side.m_WS;
+                               if (register_ifc.op_side.m_AA == 1'b1) 
+                                       r_int_TAn <= 1'b1;
+                               r_burst_cnt <= r_burst_cnt -1;
+                       end
+                       else begin
+                               r_WS_cnt <= r_WS_cnt - 1;
+                       end
+               end
+       end
+       else if (r_burst_cnt == 2'b00) begin 
+               flexbus_state <= FlexBus_S4_HOLD;
+               if (r_R_Wn == 1'b1) begin
+                       if (r_arsize == 2'b00) begin
+                                       if (r_PS == 2'b01) begin 
+                                       r_rd_data_32bit_byte4 <= r_din[7:0];
+                               end
+                                       else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
+                                       r_rd_data_32bit_byte3 <= r_din[7:0];
+                                       r_rd_data_32bit_byte4 <= r_din[15:8];
+                               end
+                               else begin
+                                       r_rd_data_32bit_byte1 <= r_din[7:0];
+                                       r_rd_data_32bit_byte2 <= r_din[15:8];
+                                       r_rd_data_32bit_byte3 <= r_din[23:16];
+                                       r_rd_data_32bit_byte4 <= r_din[31:24];
+                               end
+                       end
+                       else if (r_arsize == 2'b10) begin
+                               if (r_PS == 2'b01)
+                                       r_rd_data_32bit_byte2 <= r_din[7:0];
+                                       //if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
+                               else begin
+                                       r_rd_data_32bit_byte1 <= r_din[7:0];
+                                       r_rd_data_32bit_byte2 <= r_din[15:8];
+                               end
+                       end
+                       else if (r_arsize == 2'b01) begin
+                               r_rd_data_32bit_byte1 <= r_din[7:0];
+                       end
+                       r_rready <= True;
+               end
+               if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now 
+                       r_OEn <= 1'b1;
+                       r_BE_BWEn <= 4'hF;
+                       r_FBCSn <= 6'h3F;
+               end
+       end
+   endrule
+
+   rule rl_state_S4_HOLD (flexbus_state == FlexBus_S4_HOLD); //Address Phase
+       `ifdef verbose_debug $display("STATE S4 FIRED");`endif
+       r_int_TAn <= 1'b1;
+       r_R_Wn <= 1'b1;
+       r_OEn <= 1'b1;
+       r_BE_BWEn <= 4'hF;
+       r_FBCSn <= 6'h3F;
+       r_TBSTn <= 1'b1;
+        if (r_hld_cnt ==  2'b00) begin
+            if (wr_pending == 1'b1) begin
+                flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
+                   flexbus_state_wr <= IDLE;
+                   flexbus_state_rd <= IDLE;
+                wr_pending <= 1'b0;
+            end
+            else begin
+                flexbus_state <= IDLE;
+                   flexbus_state_wr <= FlexBus_S0_CHK_FIFOS;
+                   flexbus_state_rd <= FlexBus_S0_CHK_FIFOS;
+            end
+                r1_arvalid  <= False;
+                r1_awvalid  <= False;
+                r1_wvalid   <= False;
+
+                       r_rready        <= False;
+                r_wrbresp      <= AXI4_OKAY;  
+                r_rresp            <= AXI4_OKAY;  
+                r_ASET         <= 2'b00;  
+                r_rpt_cnt      <= 3'b000;  
+                r_burst_cnt    <= 2'b00;  
+                r_hld_cnt      <= 2'b00;  
+                r_WS_cnt       <= 6'h00;  
+                r_SWS_cnt      <= 6'h00;  
+                r_awaddr        <= 0;
+                r_wdata         <= 0;
+                //r_rd_data     <= 0;
+                r1_wstrb       <= 0;
+                //r2_wstrb     <= 0;
+                r_araddr        <= 0;
+        end
+        else 
+               r_hld_cnt <= r_hld_cnt -1;
+   endrule
+
+   // ----------------------------------------------------------------
+   // INTERFACE
+
+   method Action reset;
+      `ifdef verbose_debug_l2 $display (" I RESET \n"); `endif
+      f_wr_addr.clear;
+      f_wr_data.clear;
+      f_wr_resp.clear;
+      f_rd_addr.clear;
+      f_rd_data.clear;
+      
+      c_TAn[0]<= tagged Invalid;
+      c_din[0]<= tagged Invalid;
+   endmethod
+
+   // AXI side
+   interface axi_side = interface AXI4_Slave_IFC;
+
+                          // Wr Addr channel
+                          method Action m_awvalid (Bool           awvalid,
+                                                   Bit #(wd_addr) awaddr,
+                                                               Bit#(3) awsize,
+                                                   Bit #(wd_user) awuser,
+                                                               Bit#(8) awlen,
+                                                               Bit#(2) awburst,
+                                Bit#(4) awid
+                                                               );
+                  if (awvalid && f_wr_addr.notFull) begin
+                                       f_wr_addr.enq (AXI4_Wr_Addr {awaddr: awaddr,
+                                                                  awuser: awuser,
+                                                                        awlen:awlen,
+                                                                        awsize:awsize,
+                                                                        awburst:awburst,
+                                     awid:awid});
+                    end
+                          endmethod
+
+                          method Bool m_awready;
+                             return f_wr_addr.notFull;
+                          endmethod
+
+                          // Wr Data channel
+                          method Action m_wvalid (Bool                      wvalid,
+                                                  Bit #(wd_data)            wdata,
+                                                  Bit #(TDiv #(wd_data, 8)) wstrb,
+                                                        Bool wlast,
+                                                        Bit#(4) wid);
+                             if (wvalid && f_wr_data.notFull) begin 
+                                f_wr_data.enq (AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast:wlast, wid: wid});
+                            end
+                          endmethod
+
+                          method Bool m_wready;
+                             return f_wr_data.notFull;
+                          endmethod
+
+                          // Wr Response channel
+                          method Bool           m_bvalid = f_wr_resp.notEmpty;
+                          method Bit #(2)       m_bresp  = pack (f_wr_resp.first.bresp);
+                          method Bit #(wd_user) m_buser  = f_wr_resp.first.buser;
+                          method Bit #(4)       m_bid  = f_wr_resp.first.bid;
+                          method Action m_bready (Bool bready);
+                             if (bready && f_wr_resp.notEmpty)
+                                f_wr_resp.deq;
+                          endmethod
+
+                          // Rd Addr channel
+                          method Action m_arvalid (Bool           arvalid,
+                                                   Bit #(wd_addr) araddr,
+                                                               Bit#(3)                          arsize,
+                                                   Bit #(wd_user) aruser,
+                                                               Bit#(8)                          arlen,
+                                                               Bit#(2)                          arburst,
+                                Bit#(4) arid);
+                                if (arvalid && f_rd_addr.notFull) begin
+                                f_rd_addr.enq (AXI4_Rd_Addr {araddr: araddr,
+                                                                  aruser: aruser,
+                                                                        arlen : arlen,
+                                                                        arsize: arsize,
+                                                                        arburst:arburst,
+                                     arid:arid});
+                        end
+                          endmethod
+
+                          method Bool m_arready;
+                             return f_rd_addr.notFull;
+                          endmethod
+
+                          // Rd Data channel
+                          method Bool           m_rvalid = f_rd_data.notEmpty;
+                          method Bit #(2)       m_rresp  = pack (f_rd_data.first.rresp);
+                          method Bit #(wd_data) m_rdata  = f_rd_data.first.rdata;
+                          method Bool m_rlast  = f_rd_data.first.rlast;
+                          method Bit #(wd_user) m_ruser  = f_rd_data.first.ruser;
+                          method Bit#(4) m_rid=f_rd_data.first.rid;
+
+                          method Action m_rready (Bool rready);
+                             if (rready && f_rd_data.notEmpty)
+                                f_rd_data.deq;
+                          endmethod
+                       endinterface;
+
+interface flexbus_side = interface FlexBus_Master_IFC;
+           //interface io_AD_master = tri_AD_out.io;
+        
+                         method Action m_TAn (Bit #(1) tAn) if(c_TAn[0] matches tagged Invalid);
+                               c_TAn[0] <= tagged Valid tAn;
+                         endmethod
+                          method Action m_din ( Bit#(32) din )if(c_din[0] matches tagged Invalid); 
+                               c_din[0] <= tagged Valid din;
+               endmethod
+                        method Bit #(32)   m_AD;            
+                               return r_AD;
+             endmethod
+
+
+                        method Bit #(1)       m_R_Wn;                                   // out
+                               return r_R_Wn;
+                         endmethod
+                        method Bit #(2)       m_TSIZ;                                   // out
+                               return r_TSIZ;
+                         endmethod
+
+
+
+                        method Bit #(6)       m_FBCSn;                                  // out
+                               return r_FBCSn;
+                         endmethod
+                        method Bit #(4)       m_BE_BWEn;                                // out
+                               return r_BE_BWEn;
+                         endmethod
+                        method Bit #(1)       m_TBSTn;                                  // out
+                               return r_TBSTn;
+                         endmethod
+                        method Bit #(1)       m_OEn;                                    // out
+                               return r_OEn;
+                         endmethod
+
+                        method Bit #(1)       m_ALE;                                    // out
+                               return r_ALE;
+                         endmethod
+                //endinterface;
+
+                       endinterface;
+
+endmodule: mkAXI4_Slave_to_FlexBus_Master_Xactor
+
+module mkFlexBus_Registers (FlexBus_Register_IFC);
+
+// Vectors of Chip Select AR, MR and Control Registers
+        Vector#(6, Reg#(Bit#(32)) ) vec_addr_regs <- replicateM (mkReg(0));
+        Vector#(6, Reg#(Bit#(32)) ) vec_mask_regs <- replicateM (mkReg(0));
+        Vector#(6, Reg#(Bit#(32)) ) vec_cntr_regs <- replicateM (mkReg(0));
+
+// Control Register Fields
+
+       Reg#(Bit#(6)) r_FBCSn   <- mkReg(6'h3F); 
+       Reg#(Bit#(6)) r_SWS     <- mkReg(6'h00); 
+       Reg#(Bit#(1)) r_SWS_EN  <- mkReg(1'b0); 
+       Reg#(Bit#(2)) r_ASET    <- mkReg(2'b00); 
+       Reg#(Bit#(2)) r_RDAH    <- mkReg(2'b00); 
+       Reg#(Bit#(2)) r_WRAH    <- mkReg(2'b00); 
+       Reg#(Bit#(6)) r_WS      <- mkReg(6'h00); 
+       Reg#(Bit#(1)) r_AA      <- mkReg(1'b0); 
+       Reg#(Bit#(2)) r_PS      <- mkReg(2'b00); 
+       Reg#(Bit#(1)) r_BEM     <- mkReg(1'b0); 
+       Reg#(Bit#(1)) r_BSTR    <- mkReg(1'b0); 
+       Reg#(Bit#(1)) r_BSTW    <- mkReg(1'b0);
+
+       Reg#(Bit#(32)) r_rom_cntr_reg_0 <- mkReg(0);
+       Reg#(Bit#(32)) r_ad_bus         <- mkReg(32'hFFFFFFFF);
+       Reg#(Bit#(32)) r_data_bus       <- mkReg(32'h00000000);
+       Reg#(Bit#(32)) r_MBAR           <- mkReg(32'h04000000);
+//------------------------------------------------------------------------
+
+       rule rl_write_config_regs;
+               Bit#(32) v_MBAR = r_MBAR + 'h0500;
+               for (int i=0; i<6; i=i+1) begin
+                       if ( v_MBAR == r_ad_bus) begin 
+                               vec_addr_regs[i][31:16] <= r_data_bus[31:16];
+                        end
+                       v_MBAR = v_MBAR + 'h04;
+                       if ( v_MBAR == r_ad_bus) begin
+                               vec_mask_regs[i] <= r_data_bus;
+                        end
+                       v_MBAR = v_MBAR + 'h04;
+                       if ( v_MBAR == r_ad_bus) begin
+                               vec_cntr_regs[i] <= r_data_bus;
+                        end
+                       v_MBAR = v_MBAR + 'h04;
+               end
+       endrule
+
+       rule rl_generate_individual_chip_sels;
+
+          Bit#(6) chp_sel_vec = 6'h3F;
+          Bit#(32) r_cntr_reg_sel = 32'h00000000;
+          for (int i=0; i<6; i=i+1) begin
+               if ((~vec_mask_regs[i] & vec_addr_regs[i]) == (~vec_mask_regs[i] & pack({r_ad_bus[31:16],16'h0000}))) begin
+                       chp_sel_vec[i] = 1'b0;
+               end
+           end
+          r_FBCSn <= pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]});
+
+               case (pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]})) matches
+                    {6'b111110}: r_cntr_reg_sel   = vec_cntr_regs[0];
+                    {6'b111101}: r_cntr_reg_sel   = vec_cntr_regs[1];
+                    {6'b111011}: r_cntr_reg_sel   = vec_cntr_regs[2];
+                    {6'b110111}: r_cntr_reg_sel   = vec_cntr_regs[3];
+                    {6'b101111}: r_cntr_reg_sel   = vec_cntr_regs[4];
+                    {6'b011111}: r_cntr_reg_sel   = vec_cntr_regs[5];
+               endcase
+
+               r_SWS           <= r_cntr_reg_sel[31:26];
+               r_SWS_EN        <= r_cntr_reg_sel[23];
+               r_ASET          <= r_cntr_reg_sel[21:20];
+               r_RDAH          <= r_cntr_reg_sel[19:18];
+               r_WRAH          <= r_cntr_reg_sel[17:16];
+               //r_WS                  <= r_cntr_reg_sel[15:10];
+        r_WS        <= 6'h06;
+               r_AA            <= r_cntr_reg_sel[8];
+               r_PS            <= r_cntr_reg_sel[7:6];
+               r_BEM           <= r_cntr_reg_sel[5];
+               r_BSTR          <= r_cntr_reg_sel[4];
+               r_BSTW          <= r_cntr_reg_sel[3];
+       endrule
+//-------------------------------------------------------------------------
+// FlexBus Register Input Interface
+interface inp_side = interface FlexBus_Register_Input_IFC;
+        method Action reset (Bit #(32) ad_bus);
+               for (int i=0; i<6; i=i+1)
+                    vec_addr_regs[i] <= 32'h00000000;
+               for (int i=0; i<6; i=i+1)
+                    vec_mask_regs[i] <= 32'h00000000;
+               for (int i=0; i<6; i=i+1)
+                    vec_cntr_regs[i] <= 32'h00000000;
+                r_rom_cntr_reg_0[8] <= ad_bus[2];
+                r_rom_cntr_reg_0[7:6] <= ad_bus[1:0];
+                r_rom_cntr_reg_0[5] <= ad_bus[3];
+                r_rom_cntr_reg_0[15:10] <= 6'h3F;
+                r_rom_cntr_reg_0[21:16] <= 6'h3F;
+               vec_cntr_regs[0] <= r_rom_cntr_reg_0;
+        endmethod
+        method Action m_ad_bus (Bit #(32) ad_bus);
+               r_ad_bus <= ad_bus;
+        endmethod
+        method Action m_data_bus (Bit #(32) data_bus);
+               r_data_bus <= data_bus;
+        endmethod
+       endinterface;
+
+// FlexBus Register Output Interface
+interface op_side = interface FlexBus_Register_Output_IFC;
+       method Bit#(6) m_FBCSn ();
+               return r_FBCSn;
+        endmethod
+       method Bit#(6) m_SWS ();
+               return r_SWS;
+        endmethod
+        method Bit#(1) m_SWS_EN (); 
+               return r_SWS_EN;
+        endmethod
+       method Bit#(2) m_ASET ();
+               return r_ASET;
+        endmethod
+       method Bit#(2) m_RDAH ();
+               return r_RDAH;
+        endmethod
+       method Bit#(2) m_WRAH ();
+               return r_WRAH;
+        endmethod
+       method Bit#(6) m_WS ();
+               return r_WS;
+        endmethod
+       method Bit#(1) m_AA ();
+               return r_AA;
+        endmethod
+       method Bit#(2) m_PS ();
+               return r_PS;
+        endmethod
+       method Bit#(1) m_BEM ();
+               return r_BEM;
+        endmethod
+       method Bit#(1) m_BSTR ();
+               return r_BSTR;
+        endmethod
+       method Bit#(1) m_BSTW ();
+               return r_BSTW;
+        endmethod
+       endinterface;
+
+endmodule: mkFlexBus_Registers
+
+
+endpackage
diff --git a/src/peripherals/jtagdtm/jtagdefines.bsv b/src/peripherals/jtagdtm/jtagdefines.bsv
new file mode 100644 (file)
index 0000000..83b1daf
--- /dev/null
@@ -0,0 +1,19 @@
+`define EXTEST 'h00
+`define IDCODE 'h01
+`define SAMPLE_PRELOAD 'h02
+`define SCANMODE_TE 'h03
+`define SCAN1 'h04
+`define SCAN2 'h05
+`define SCAN3 'h06
+`define SCAN4 'h07
+`define SCAN5 'h08
+`define SCANALL 'h12
+`define SCANEN 'h13
+`define FULLSCANEN 'h14
+`define DEBUG  'h0A
+`define MBIST  'h09
+`define BYPASS 'h1f
+`define DTMCONTROL 'h10
+`define DMIACCESS 'h11
+//`define IDCODEVALUE 32'h10e31913
+`define IDCODEVALUE 32'h100039D3
diff --git a/src/peripherals/jtagdtm/jtagdtm.bsv b/src/peripherals/jtagdtm/jtagdtm.bsv
new file mode 100644 (file)
index 0000000..aea5b37
--- /dev/null
@@ -0,0 +1,568 @@
+/*
+Copyright (c) 2013, IIT Madras
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+*  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+*  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+*  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+package jtagdtm;
+/*====== Package imports ======= */
+       import Clocks::*;
+       import ConcatReg::*;
+       import FIFO::*;
+       import FIFOF::*;
+       import SpecialFIFOs::*;
+       import DReg::*;
+/*======= Project imports ===== */
+       `include "jtagdefines.bsv"
+       import defined_types::*;
+/*============================== */
+
+interface Ifc_jtagdtm;
+       /*======== Scan input pins ===== */
+       (*always_enabled,always_ready*)
+       method Action scan_out_1_i(Bit#(1) scan_out_1);
+       (*always_enabled,always_ready*)
+       method Action scan_out_2_i(Bit#(1) scan_out_2);
+       (*always_enabled,always_ready*)
+       method Action scan_out_3_i(Bit#(1) scan_out_3);
+       (*always_enabled,always_ready*)
+       method Action scan_out_4_i(Bit#(1) scan_out_4);
+       (*always_enabled,always_ready*)
+       method Action scan_out_5_i(Bit#(1) scan_out_5);
+       /*======= SCAN Output Pins ====== */
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_in_1;
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_in_2;
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_in_3;
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_in_4;
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_in_5;
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_en;
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_mode_te;
+       /*======= BOUNDARY SCAN Output Pin ====== */
+       (*always_enabled,always_ready*)
+       method Action bs_chain_i(Bit#(1) bs_chain);
+       /*======= BOUNDARY SCAN input Pins ====== */
+       (*always_enabled,always_ready*)
+    method Bit#(1) shiftBscan2Edge;
+       (*always_enabled,always_ready*)
+    method Bit#(1) selectJtagInput;
+       (*always_enabled,always_ready*)
+    method Bit#(1) selectJtagOutput;
+       (*always_enabled,always_ready*)
+    method Bit#(1) updateBscan;
+       (*always_enabled,always_ready*)
+       method Bit#(1) bscan_in;
+       (*always_enabled,always_ready*)
+       method Bit#(1) scan_shift_en;
+       /*======== JTAG input pins ===== */
+       (*always_enabled,always_ready*)
+       method Action tms_i(Bit#(1) tms);
+       (*always_enabled,always_ready*)
+       method Action tdi_i(Bit#(1) tdi);
+       /*==== inputs from Sub-modules === */
+       method Action debug_tdi_i(Bit#(1) debug_tdi);
+       /*======= JTAG Output Pins ====== */
+       (*always_enabled,always_ready*)
+       method Bit#(1) tdo;
+       method Bit#(1) tdo_oe;
+       /*======== TAP States ============= */
+       method Bit#(1) shift_dr;
+       method Bit#(1) pause_dr;
+       method Bit#(1) update_dr;
+       method Bit#(1) capture_dr;
+       /*=========== Output for BS Chain ==== */
+       method Bit#(1) extest_select;
+       method Bit#(1) sample_preload_select;
+       method Bit#(1) debug_select;
+       method Bit#(1) debug_tdo;
+       /*================================ */
+       method Action response_from_dm(Bit#(34) responsedm);
+       method ActionValue#(Bit#(40)) request_to_dm;
+
+endinterface
+  
+  function Reg#(t) readOnlyReg(t r);
+    return (interface Reg;
+       method t _read = r;
+       method Action _write(t x) = noAction;
+    endinterface);
+  endfunction
+       function Reg#(Bit#(1)) condwriteSideEffect(Reg#(Bit#(1)) r, Action a);
+               return (interface Reg;
+            method Bit#(1) _read = r._read;
+            method Action _write(Bit#(1) x);
+                r._write(x);
+                                        if(x==1)
+                                               a;
+            endmethod
+        endinterface);
+       endfunction
+       
+
+
+typedef enum {TestLogicReset = 4'h0,  RunTestIdle    = 4'h1,  SelectDRScan   = 4'h2,
+      CaptureDR      = 4'h3,  ShiftDR        = 4'h4,  Exit1DR        = 4'h5,
+      PauseDR        = 4'h6,  Exit2DR        = 4'h7,  UpdateDR       = 4'h8,
+      SelectIRScan   = 4'h9,  CaptureIR      = 4'ha,  ShiftIR        = 4'hb,
+      Exit1IR        = 4'hc,  PauseIR        = 4'hd,  Exit2IR        = 4'he,
+      UpdateIR       = 4'hf } TapStates deriving(Bits,Eq,FShow);
+
+       (*synthesize*)
+       (*descending_urgency="scan_logic,scan_shift_en"*)
+       module mkjtagdtm(Ifc_jtagdtm);
+       Clock def_clk<-exposeCurrentClock;
+       Clock invert_clock<-invertCurrentClock;
+       Reset invert_reset<-mkAsyncResetFromCR(0,invert_clock);
+       
+       /*========= FIFOs to communicate with the DM==== */
+       FIFOF#(Bit#(40)) request_to_DM <-mkUGFIFOF1();
+       FIFOF#(Bit#(34)) response_from_DM <-mkUGFIFOF1();
+       /*================================================ */
+
+       /*=== Wires to capture the input pins === */
+       Wire#(Bit#(1)) wr_tms<-mkDWire(0);
+       Wire#(Bit#(1)) wr_tdi<-mkDWire(0);
+       Reg#(Bit#(1)) wr_debug_tdi<-mkRegA(0);
+       Reg#(Bit#(1)) wr_bs_chain_tdo<-mkRegA(0);
+       /*======================================== */
+       
+       Wire#(Bit#(1)) wr_scan_in_1_all <-mkDWire(0);
+       Wire#(Bit#(1)) wr_scan_in_2_out1 <-mkDWire(0);
+       Wire#(Bit#(1)) wr_scan_in_3_out2 <-mkDWire(0);
+       Wire#(Bit#(1)) wr_scan_in_4_out3 <-mkDWire(0);
+       Wire#(Bit#(1)) wr_scan_in_5_out4 <-mkDWire(0);
+       Reg#(Bit#(1)) wr_scan_shift_en[2] <-mkCRegA(2,0);
+
+       Reg#(TapStates) tapstate<-mkRegA(TestLogicReset);
+       Reg#(Bit#(5)) instruction_shiftreg<-mkRegA(0);
+       Reg#(Bit#(5)) instruction<-mkRegA(`IDCODE, clocked_by invert_clock, reset_by invert_reset); // clock this by the inverted clock
+       Reg#(Bit#(1)) bypass_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan1_sr <-mkRegA(0);
+       Reg#(Bit#(1)) scan2_sr <-mkRegA(0);
+       Reg#(Bit#(1)) scan3_sr <-mkRegA(0);
+       Reg#(Bit#(1)) scan4_sr <-mkRegA(0);
+       Reg#(Bit#(1)) scan5_sr <-mkRegA(0);
+       Reg#(Bit#(1)) scanall_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan_en_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan_mode_te_sr<-mkRegA(0);
+       Reg#(Bit#(1)) full_scan_en_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan_out_1_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan_out_2_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan_out_3_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan_out_4_sr<-mkRegA(0);
+       Reg#(Bit#(1)) scan_out_5_sr<-mkRegA(0);
+    Wire#(Bit#(1)) shiftBscan2Edge_sr<-mkDWire(0);  
+    Wire#(Bit#(1)) selectJtagInput_sr<-mkDWire(0);
+    Wire#(Bit#(1)) selectJtagOutput_sr<-mkDWire(0);
+    Wire#(Bit#(1)) updateBscan_sr<-mkDWire(0);
+    Reg#(Bit#(1)) bs_sr<-mkRegA(0);
+       Reg#(Bit#(32)) idcode_sr<-mkRegA(`IDCODEVALUE);
+
+       Wire#(Bool)             wr_dmihardreset_generated<-mkDWire(False);
+       Reg#(Bit#(1))   rg_dmihardreset<-mkRegA(0);
+       Reg#(Bit#(1))   dmihardreset=condwriteSideEffect(rg_dmihardreset,wr_dmihardreset_generated._write(True));
+       Wire#(Bool)             wr_dmireset_generated<-mkDWire(False);
+       Reg#(Bit#(1))   rg_dmireset<-mkDReg(0);
+       Reg#(Bit#(1))   dmireset=condwriteSideEffect(rg_dmireset,wr_dmireset_generated._write(True));
+       Reg#(Bit#(3))   idle=readOnlyReg(3'd7);
+       Reg#(Bit#(2))   dmistat<-mkRegA(0);
+       Reg#(Bit#(6))   abits =readOnlyReg(6'd6);
+       Reg#(Bit#(4))   version = readOnlyReg('d1);
+       Reg#(Bit#(32)) dtmcontrol=concatReg8(readOnlyReg(14'd0),
+               dmihardreset,dmireset,readOnlyReg(1'd0),
+               idle,readOnlyReg(dmistat),abits,version);
+       Reg#(Bit#(32)) dtmcontrol_shiftreg<-mkRegA({17'd0,3'd7,2'd0,6'd6,4'd1});
+
+       Reg#(Bit#(40)) dmiaccess_shiftreg[2]<-mkCReg(2,'d2);
+       Reg#(Bit#(2))   response_status<-mkReg(0);
+       Reg#(Bool)              capture_repsonse_from_dm<-mkRegA(False);
+       Reg#(Bit#(1)) rg_tdo<-mkRegA(0, clocked_by invert_clock, reset_by invert_reset);
+
+       ReadOnly#(TapStates) crossed_tapstate           <-mkNullCrossingWire(invert_clock,tapstate);
+       ReadOnly#(Bit#(5))      crossed_instruction_shiftreg<-mkNullCrossingWire(invert_clock,instruction_shiftreg);
+       ReadOnly#(Bit#(5))      crossed_instruction     <-mkNullCrossingWire(def_clk,instruction);
+       ReadOnly#(Bit#(1))      crossed_scan_out_1_sr   <-mkNullCrossingWire(invert_clock,scan_out_1_sr);
+       ReadOnly#(Bit#(1))      crossed_scan_out_2_sr   <-mkNullCrossingWire(invert_clock,scan_out_2_sr);
+       ReadOnly#(Bit#(1))      crossed_scan_out_3_sr   <-mkNullCrossingWire(invert_clock,scan_out_3_sr);
+       ReadOnly#(Bit#(1))      crossed_scan_out_4_sr   <-mkNullCrossingWire(invert_clock,scan_out_4_sr);
+       ReadOnly#(Bit#(1))      crossed_scan_out_5_sr   <-mkNullCrossingWire(invert_clock,scan_out_5_sr);
+       ReadOnly#(Bit#(1))      crossed_scan_en_sr              <-mkNullCrossingWire(invert_clock,scan_en_sr);
+       ReadOnly#(Bit#(1))      crossed_scan_mode_te_sr <-mkNullCrossingWire(invert_clock,scan_mode_te_sr);
+       ReadOnly#(Bit#(1))      crossed_full_scan_en_sr <-mkNullCrossingWire(invert_clock,full_scan_en_sr);
+       ReadOnly#(Bit#(1))      crossed_bypass_sr               <-mkNullCrossingWire(invert_clock,bypass_sr);
+       ReadOnly#(Bit#(32))     crossed_idcode_sr               <-mkNullCrossingWire(invert_clock,idcode_sr);
+       ReadOnly#(Bit#(1))      crossed_bs_chain_tdo    <-mkNullCrossingWire(invert_clock,wr_bs_chain_tdo);
+       ReadOnly#(Bit#(1))      crossed_debug_tdi               <-mkNullCrossingWire(invert_clock,wr_debug_tdi);
+       ReadOnly#(Bit#(32))     crossed_dtmcontrol_shiftreg<-mkNullCrossingWire(invert_clock,dtmcontrol_shiftreg);
+       ReadOnly#(Bit#(1)) crossed_output_tdo<-mkNullCrossingWire(def_clk,rg_tdo);
+       ReadOnly#(Bit#(40)) crossed_dmiaccess_shiftreg<-mkNullCrossingWire(invert_clock,dmiaccess_shiftreg[0]);
+
+   Bit#(1) bypass_sel   = crossed_instruction == `BYPASS?1:0;
+   Bit#(1) scan_en_sel   = crossed_instruction == `SCANEN?1:0;
+   Bit#(1) scan_mode_te_sel   = crossed_instruction == `SCANMODE_TE?1:0;
+   Bit#(1) scan1_sel    = crossed_instruction == `SCAN1?1:0;
+   Bit#(1) scan2_sel    = crossed_instruction == `SCAN2?1:0;
+   Bit#(1) scan3_sel    = crossed_instruction == `SCAN3?1:0;
+   Bit#(1) scan4_sel    = crossed_instruction == `SCAN4?1:0;
+   Bit#(1) scan5_sel    = crossed_instruction == `SCAN5?1:0;
+   Bit#(1) scanall_sel  = crossed_instruction == `SCANALL?1:0;
+   Bit#(1) full_scan_en_sel  = crossed_instruction == `FULLSCANEN?1:0;
+   Bit#(1) idcode_sel   = crossed_instruction == `IDCODE?1:0;
+   Bit#(1) dbg_sel      = crossed_instruction == `DEBUG?1:0;
+   Bit#(1) dtmcontrol_sel  = crossed_instruction == `DTMCONTROL?1:0;
+   Bit#(1) dmi_sel      = crossed_instruction == `DMIACCESS?1:0;
+   Bit#(1) extest_select=crossed_instruction==`EXTEST?1:0;
+   Bit#(1) sample_preload_select=crossed_instruction==`SAMPLE_PRELOAD?1:0;
+
+       Bit#(1) instruction_tdo=crossed_instruction_shiftreg[0];
+       Bit#(1) bypass_tdo=crossed_bypass_sr;
+       Bit#(1) scan_en_tdo=crossed_scan_en_sr;
+       Bit#(1) scan_mode_te_tdo=crossed_scan_mode_te_sr;
+       Bit#(1) full_scan_en_tdo=crossed_full_scan_en_sr;
+       Bit#(1) scan_out_1_tdo=crossed_scan_out_1_sr;
+       Bit#(1) scan_out_2_tdo=crossed_scan_out_2_sr;
+       Bit#(1) scan_out_3_tdo=crossed_scan_out_3_sr;
+       Bit#(1) scan_out_4_tdo=crossed_scan_out_4_sr;
+       Bit#(1) scan_out_5_tdo=crossed_scan_out_5_sr;
+       Bit#(1) idcode_tdo=crossed_idcode_sr[0];
+       Bit#(1) dtmcontrol_tdo=crossed_dtmcontrol_shiftreg[0];
+       Bit#(1) dmiaccess_tdo=crossed_dmiaccess_shiftreg[0][0];
+
+       
+
+       /*== This rule implements the TAPs STATE MACHINE====== */
+       rule just_display;
+               `ifdef verbose $display($time,"\tTAPSTATE: ",fshow(tapstate),"\tINSTRUCTION: %h",instruction_shiftreg); `endif
+       endrule
+       rule tap_state_machine;
+               case(tapstate)
+                       TestLogicReset: if(wr_tms==0) tapstate<=RunTestIdle;
+         RunTestIdle   : if(wr_tms==1) tapstate <= SelectDRScan;
+         SelectDRScan  : if(wr_tms==1) tapstate <= SelectIRScan;
+                         else          tapstate <= CaptureDR;
+         CaptureDR     : if(wr_tms==0) tapstate <= ShiftDR;
+                         else          tapstate <= Exit1DR;
+         ShiftDR       : if(wr_tms==1) tapstate <= Exit1DR;
+         Exit1DR       : if(wr_tms==0) tapstate <= PauseDR;
+                         else          tapstate <= UpdateDR;
+         PauseDR       : if(wr_tms==1) tapstate <= Exit2DR;
+         Exit2DR       : if(wr_tms==1) tapstate <= UpdateDR;
+                         else          tapstate <= ShiftDR;
+         UpdateDR      : if(wr_tms==1) tapstate <= SelectDRScan;
+                         else          tapstate <= RunTestIdle;
+         SelectIRScan  : if(wr_tms==1) tapstate <= TestLogicReset;
+                         else          tapstate <= CaptureIR;
+         CaptureIR     : if(wr_tms==0) tapstate <= ShiftIR;
+                         else          tapstate <= Exit1IR;
+         ShiftIR       : if(wr_tms==1) tapstate <= Exit1IR;
+         Exit1IR       : if(wr_tms==0) tapstate <= PauseIR;
+                         else          tapstate <= UpdateIR;
+         PauseIR       : if(wr_tms==1) tapstate <= Exit2IR;
+         Exit2IR       : if(wr_tms==1) tapstate <= UpdateIR;
+                         else          tapstate <= ShiftIR;
+         UpdateIR      : if(wr_tms==1) tapstate <= SelectDRScan;
+                         else          tapstate <= RunTestIdle;
+         default       :               tapstate <= TestLogicReset;
+               endcase
+       endrule
+
+       rule dmireset_generated(wr_dmireset_generated);
+               `ifdef verbose $display($time,"\tDTM: Received DMIRESET"); `endif
+               dmiaccess_shiftreg[1][1:0]<='d0;
+               response_status<=0;
+               capture_repsonse_from_dm<=False;
+       endrule
+       rule dmihardreset_generated(wr_dmihardreset_generated);
+               request_to_DM.deq;
+               response_from_DM.deq;
+               capture_repsonse_from_dm<=False;
+       endrule
+
+       /*======= perform dtmcontrol shifts ======== */
+       rule shift_dtm;
+               case(tapstate)
+                       TestLogicReset: dtmcontrol<={17'd0,idle,2'b0,abits,version};
+                       CaptureDR:      if(dtmcontrol_sel==1) dtmcontrol_shiftreg<=dtmcontrol;
+                       ShiftDR:                if(dtmcontrol_sel==1) dtmcontrol_shiftreg<={wr_tdi,dtmcontrol_shiftreg[31:1]};
+                       UpdateDR:       if(dtmcontrol_sel==1) dtmcontrol<=dtmcontrol_shiftreg;
+               endcase
+       endrule
+       /*========================================== */
+       /*======= perform dmiaccess shifts ======== */
+       rule shift_dmiaccess(!wr_dmihardreset_generated);
+               case(tapstate)
+                       TestLogicReset: dmiaccess_shiftreg[0]<='d0;
+                       CaptureDR:      if(dmi_sel==1) 
+                               if(response_from_DM.notEmpty)begin 
+                                       let x=response_from_DM.first[33:0];
+                                       `ifdef verbose $display($time,"\tDTM: Getting response: data %h op: %h",x[33:2],x[1:0]); `endif
+                                       x[1:0]=x[1:0]|response_status;// keeping the lower 2 bits sticky
+                                       dmiaccess_shiftreg[0][33:0]<=x; 
+                                       response_status<=x[1:0];
+                                       response_from_DM.deq; 
+                                       `ifdef verbose $display($time,"\tDTM: New DMIACCESS value: %h",x); `endif
+                                       capture_repsonse_from_dm<=False;
+                                       dmistat<=x[1:0];
+                               end
+                               else begin
+                                       if(capture_repsonse_from_dm)
+                                               response_status<=3;
+                                       `ifdef verbose $display($time,"\tDTM: RESPONSE NOT AVAILABLE. DMIACCESS: %h",dmiaccess_shiftreg[0]); `endif
+                               end
+                       ShiftDR:                if(dmi_sel==1) dmiaccess_shiftreg[0]<={wr_tdi,dmiaccess_shiftreg[0][39:1]};
+                       UpdateDR:       if(dmi_sel==1) 
+                               if(request_to_DM.notFull && dmiaccess_shiftreg[0][1:0]!=0 && capture_repsonse_from_dm==False)begin
+                                       request_to_DM.enq(dmiaccess_shiftreg[0]);
+                                       dmiaccess_shiftreg[0][1:0]<='d3;
+                                       capture_repsonse_from_dm<=True;
+                                       `ifdef verbose $display($time,"\tDTM: Sending request to Debug: %h",dmiaccess_shiftreg[0]); `endif
+                               end
+                               else begin
+                                       `ifdef verbose $display($time,"\tDTM: REQUEST NOT SERVED capture: %b DMIACCESS: %h",capture_repsonse_from_dm,dmiaccess_shiftreg[0]); `endif
+//                                     dmistat<=3;
+//                                     response_from_DM.enq('d3);
+                               end
+               endcase
+       endrule
+       /*========================================== */
+
+       /*== perform instruction register shifts === */
+       rule shift_reg;
+               case(tapstate)
+                       CaptureIR:      instruction_shiftreg<='b10101;
+                       ShiftIR  :      instruction_shiftreg<= {wr_tdi,instruction_shiftreg[4:1]};
+               endcase
+       endrule
+       rule transfer_instruction_on_nedge; // TODO negedge here
+               case(crossed_tapstate)
+                       TestLogicReset  :instruction<=`IDCODE;
+                       UpdateIR                        :instruction<=crossed_instruction_shiftreg;
+               endcase
+       endrule
+
+       /*==== Bypass Section === */
+       rule bypass_logic;
+               case(tapstate)
+                       TestLogicReset: bypass_sr<=1'b0;
+                       CaptureDR         : if(bypass_sel==1) bypass_sr<=1'b0;
+                       ShiftDR           : if(bypass_sel==1) bypass_sr<=wr_tdi;
+               endcase
+       endrule
+
+       /*==== Boundary Scan Section === */
+       rule bs_logic;
+               case(tapstate)
+                       TestLogicReset: bs_sr<=1'b0;
+                       CaptureDR         : begin
+                                if(extest_select==1) begin 
+                                    shiftBscan2Edge_sr <= 1'b0;
+                                    selectJtagInput_sr <= 1'b0;
+                                    selectJtagOutput_sr <= 1'b0;
+                                    updateBscan_sr <= 1'b0;
+                                    bs_sr<=1'b0;
+                                end else if (sample_preload_select ==1) begin
+                                    shiftBscan2Edge_sr <= 1'b0;
+                                    selectJtagInput_sr <= 1'b0;
+                                    selectJtagOutput_sr <= 1'b0;
+                                    bs_sr<=1'b0;
+                                end
+                            end
+                       ShiftDR           : begin
+                                if(extest_select==1) begin 
+                                    shiftBscan2Edge_sr <= 1'b1;
+                                    selectJtagInput_sr <= 1'b0;
+                                    selectJtagOutput_sr <= 1'b0;
+                                    updateBscan_sr <= 1'b0;
+                                    bs_sr<=wr_tdi;
+                                end else if (sample_preload_select ==1) begin
+                                    bs_sr<=wr_tdi;
+                                    shiftBscan2Edge_sr <= 1'b1;
+                                end 
+                            end
+            UpdateDR      : begin
+                                if(extest_select==1) begin 
+                                    shiftBscan2Edge_sr <= 1'b1;
+                                    selectJtagInput_sr <= 1'b1;
+                                    selectJtagOutput_sr <= 1'b1;
+                                    updateBscan_sr <= 1'b1;
+                                end 
+                            end
+               endcase
+       endrule
+
+       /*==== Scan Chain Section === */
+       rule scan_logic;
+               case(tapstate)
+            TestLogicReset: begin
+                                scan_en_sr<=1'b0;
+                                scan_mode_te_sr<=1'b0;
+                                scan1_sr<=1'b0;
+                                scan2_sr<=1'b0;
+                                scan3_sr<=1'b0;
+                                scan4_sr<=1'b0;
+                                scan5_sr<=1'b0;
+                                scanall_sr<=1'b0;
+                                full_scan_en_sr<=1'b0;
+                                                                                                                               wr_scan_shift_en[0]<=1'b0;
+                            end
+            CaptureDR    : begin
+                                if(scan_en_sel==1) scan_en_sr<=1'b0;
+                                else if(scan_mode_te_sel==1) scan_mode_te_sr<=1'b0;
+                                else if(scan1_sel==1) scan1_sr<=1'b0;
+                                else if(scan2_sel==1) scan2_sr<=1'b0;
+                                else if(scan3_sel==1) scan3_sr<=1'b0;
+                                else if(scan4_sel==1) scan4_sr<=1'b0;
+                                else if(scan5_sel==1) scan5_sr<=1'b0;
+                                else if(scanall_sel==1) scanall_sr<=1'b0;
+                                else if(full_scan_en_sel==1) full_scan_en_sr<=1'b0;
+                                                                                                                               wr_scan_shift_en[0]<=1'b0;
+                            end
+            ShiftDR              : begin
+                                if(scan_en_sel==1) scan_en_sr<=wr_tdi;
+                                else if(scan_mode_te_sel==1) scan_mode_te_sr<=wr_tdi;
+                                else if(scan1_sel==1) scan1_sr<=wr_tdi;
+                                else if(scan2_sel==1) scan2_sr<=wr_tdi;
+                                else if(scan3_sel==1) scan3_sr<=wr_tdi;
+                                else if(scan4_sel==1) scan4_sr<=wr_tdi;
+                                else if(scan5_sel==1) scan5_sr<=wr_tdi;
+                                else if(scanall_sel==1) scanall_sr<=wr_tdi;
+                                else if(full_scan_en_sel==1) full_scan_en_sr<=wr_tdi;
+                                if ((scan1_sel == 1'b1 || scan2_sel  == 1'b1|| scan3_sel  == 1'b1|| scan4_sel  == 1'b1|| scan5_sel  == 1'b1|| scanall_sel == 1'b1) || (scan_en_sel == 1'b1 && wr_tdi == 1'b0)) wr_scan_shift_en[1] <=1'b1;
+                            end
+            UpdateDR             : wr_scan_shift_en[0] <=1'b0;
+               endcase
+       endrule
+    
+       rule full_scan_mux_logic;
+        if (full_scan_en_sr == 1'b1) begin
+               wr_scan_in_1_all <= scanall_sr;
+               wr_scan_in_2_out1 <= scan_out_1_sr;
+               wr_scan_in_3_out2 <= scan_out_2_sr;
+               wr_scan_in_4_out3 <= scan_out_3_sr;
+               wr_scan_in_5_out4 <= scan_out_4_sr;
+        end
+        else begin
+               wr_scan_in_1_all <= scan1_sr;
+               wr_scan_in_2_out1 <= scan2_sr;
+               wr_scan_in_3_out2 <= scan3_sr;
+               wr_scan_in_4_out3 <= scan4_sr;
+               wr_scan_in_5_out4 <= scan5_sr;
+        end
+       endrule
+
+       /*======= IDCODE section === */
+       rule idcode_logic;
+               case(tapstate)
+                       TestLogicReset:idcode_sr<=`IDCODEVALUE;
+                       CaptureDR:      if(idcode_sel==1) idcode_sr<=`IDCODEVALUE;
+                       ShiftDR :   if(idcode_sel==1) idcode_sr<={wr_tdi,idcode_sr[31:1]};
+               endcase
+       endrule
+
+       rule generate_tdo_outputpin;
+               if(crossed_tapstate==ShiftIR)
+                       rg_tdo<=instruction_tdo;
+               else
+                       case(instruction)
+                               `IDCODE: rg_tdo<=idcode_tdo;
+                               `DEBUG : rg_tdo<=crossed_debug_tdi;
+                               `EXTEST: rg_tdo<=crossed_bs_chain_tdo;
+                               `SAMPLE_PRELOAD: rg_tdo<=crossed_bs_chain_tdo;
+                               `BYPASS: rg_tdo<=bypass_tdo;
+                               `SCANEN: rg_tdo<=scan_en_tdo;
+                               `SCANMODE_TE: rg_tdo<=scan_mode_te_tdo;
+                               `FULLSCANEN: rg_tdo<=full_scan_en_tdo;
+                `SCAN1: rg_tdo <= scan_out_1_tdo;
+                `SCAN2: rg_tdo <= scan_out_2_tdo;
+                `SCAN3: rg_tdo <= scan_out_3_tdo;
+                `SCAN4: rg_tdo <= scan_out_4_tdo;
+                `SCAN5: rg_tdo <= scan_out_5_tdo;
+                `SCANALL: rg_tdo <= scan_out_5_tdo;
+                               `DTMCONTROL: rg_tdo<=dtmcontrol_tdo;
+                               `DMIACCESS: rg_tdo<=dmiaccess_tdo;
+                               default:        rg_tdo<=bypass_tdo;
+                       endcase
+       endrule
+
+       /*======== SCAN input (scan chain outputs) pins ===== */
+       method Action scan_out_1_i(Bit#(1) scan_out_1);
+               scan_out_1_sr<=scan_out_1;
+       endmethod
+       method Action scan_out_2_i(Bit#(1) scan_out_2);
+               scan_out_2_sr<=scan_out_2;
+       endmethod
+       method Action scan_out_3_i(Bit#(1) scan_out_3);
+               scan_out_3_sr<=scan_out_3;
+       endmethod
+       method Action scan_out_4_i(Bit#(1) scan_out_4);
+               scan_out_4_sr<=scan_out_4;
+       endmethod
+       method Action scan_out_5_i(Bit#(1) scan_out_5);
+               scan_out_5_sr<=scan_out_5;
+       endmethod
+       /*======== JTAG input pins ===== */
+       method Action tms_i(Bit#(1) tms);
+               wr_tms<=tms;
+       endmethod
+       method Action tdi_i(Bit#(1) tdi);
+               wr_tdi<=tdi;
+       endmethod
+       /*============================= */
+       method Action debug_tdi_i(Bit#(1) debug_tdi);
+               wr_debug_tdi<=debug_tdi;
+       endmethod
+       /*======= Boundary Scan Input Pins ====== */
+       method Action bs_chain_i(Bit#(1) bs_chain);
+               wr_bs_chain_tdo<=bs_chain;
+       endmethod
+       /*======== TAP States ============= */
+       method shift_dr=tapstate==ShiftDR?1:0;
+       method pause_dr=tapstate==PauseDR?1:0;
+       method update_dr=tapstate==UpdateDR?1:0;
+       method capture_dr=tapstate==CaptureDR?1:0;
+       /*=================================== */
+       method debug_select                             =crossed_instruction==`DEBUG?1:0;
+       /*================================ */
+       /*======= SCAN Output (Scan Chain Inputs) Pins ====== */
+       method scan_in_1 = wr_scan_in_1_all;
+       method scan_in_2 = wr_scan_in_2_out1;
+       method scan_in_3 = wr_scan_in_3_out2;
+       method scan_in_4 = wr_scan_in_4_out3;
+       method scan_in_5 = wr_scan_in_5_out4;
+       method scan_en   = scan_en_sr;
+       method scan_mode_te = scan_mode_te_sr;
+       /*======= Boundary Scan Output Pins ====== */
+    method shiftBscan2Edge = shiftBscan2Edge_sr;
+    method selectJtagInput = selectJtagInput_sr;
+    method selectJtagOutput = selectJtagOutput_sr;
+    method updateBscan = updateBscan_sr;
+       method bscan_in   = bs_sr;
+       method scan_shift_en = wr_scan_shift_en[1];
+       /*======= JTAG Output Pins ====== */
+       method tdo = crossed_output_tdo;
+       method debug_tdo = wr_tdi;
+       method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
+       method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull);
+               if(capture_repsonse_from_dm)
+                       response_from_DM.enq(responsedm);
+       endmethod
+       method ActionValue#(Bit#(40)) request_to_dm if(request_to_DM.notEmpty);
+               request_to_DM.deq;
+               return request_to_DM.first;
+       endmethod
+       endmodule
+
+endpackage
diff --git a/src/peripherals/jtagdtm/jtagdtm_new.bsv b/src/peripherals/jtagdtm/jtagdtm_new.bsv
new file mode 100644 (file)
index 0000000..ae22304
--- /dev/null
@@ -0,0 +1,337 @@
+/*
+Copyright (c) 2013, IIT Madras
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+*  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+*  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+*  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+package jtagdtm_new;
+/*====== Package imports ======= */
+       import ConcatReg::*;
+       import FIFO::*;
+       import FIFOF::*;
+       import SpecialFIFOs::*;
+/*======= Project imports ===== */
+       `include "jtagdefines.bsv"
+       import defined_types::*;
+/*============================== */
+
+interface Ifc_jtagdtm;
+       /*======== JTAG input pins ===== */
+       (*always_enabled,always_ready*)
+       method Action tms_i(Bit#(1) tms);
+       (*always_enabled,always_ready*)
+       method Action tdi_i(Bit#(1) tdi);
+       (*always_enabled,always_ready*)
+       method Action tck_i(Bit#(1) tck);
+       (*always_enabled,always_ready*)
+       method Action trst_i(Bit#(1) trst);
+       /*==== inputs from Sub-modules === */
+       method Action debug_tdi_i(Bit#(1) debug_tdi);
+       method Action bs_chain_i(Bit#(1) bs_chain);
+       /*======= JTAG Output Pins ====== */
+       (*always_enabled,always_ready*)
+       method Bit#(1) tdo;
+       method Bit#(1) tdo_oe;
+       /*======== TAP States ============= */
+       method Bit#(1) shift_dr;
+       method Bit#(1) pause_dr;
+       method Bit#(1) update_dr;
+       method Bit#(1) capture_dr;
+       /*=========== Output for BS Chain ==== */
+       method Bit#(1) extest_select;
+       method Bit#(1) sample_preload_select;
+       method Bit#(1) debug_select;
+       method Bit#(1) debug_tdo;
+       /*================================ */
+       method Action response_from_dm(Bit#(34) responsedm);
+       method ActionValue#(Bit#(40)) request_to_dm;
+
+endinterface
+  
+  function Reg#(t) readOnlyReg(t r);
+    return (interface Reg;
+       method t _read = r;
+       method Action _write(t x) = noAction;
+    endinterface);
+  endfunction
+       function Reg#(Bit#(1)) condwriteSideEffect(Reg#(Bit#(1)) r, Action a);
+               return (interface Reg;
+            method Bit#(1) _read = r._read;
+            method Action _write(Bit#(1) x);
+                r._write(x);
+                                        if(x==1)
+                                               a;
+            endmethod
+        endinterface);
+       endfunction
+       
+
+
+typedef enum {TestLogicReset = 4'h0,  RunTestIdle    = 4'h1,  SelectDRScan   = 4'h2,
+      CaptureDR      = 4'h3,  ShiftDR        = 4'h4,  Exit1DR        = 4'h5,
+      PauseDR        = 4'h6,  Exit2DR        = 4'h7,  UpdateDR       = 4'h8,
+      SelectIRScan   = 4'h9,  CaptureIR      = 4'ha,  ShiftIR        = 4'hb,
+      Exit1IR        = 4'hc,  PauseIR        = 4'hd,  Exit2IR        = 4'he,
+      UpdateIR       = 4'hf } TapStates deriving(Bits,Eq,FShow);
+
+       (*synthesize*)
+       module mkjtagdtm(Ifc_jtagdtm);
+       Reg#(Bit#(1)) prv_clk <-mkReg(0);       
+       PulseWire posedge_clk <-mkPulseWire();
+       PulseWire negedge_clk <-mkPulseWire();
+       /*========= FIFOs to communicate with the DM==== */
+       FIFOF#(Bit#(40)) request_to_DM <-mkUGFIFOF1();
+       FIFOF#(Bit#(34)) response_from_DM <-mkUGFIFOF1();
+       /*================================================ */
+
+       /*=== Wires to capture the input pins === */
+       Wire#(Bit#(1)) wr_tms<-mkDWire(0);
+       Wire#(Bit#(1)) wr_tdi<-mkDWire(0);
+       Wire#(Bool) wr_trst<-mkDWire(False);
+       Wire#(Bit#(1)) wr_debug_tdi<-mkDWire(0);
+       Wire#(Bit#(1)) wr_bs_chain_tdi<-mkDWire(0);
+       /*======================================== */
+       
+       Reg#(TapStates) tapstate<-mkRegA(TestLogicReset);
+       Reg#(Bit#(5)) instruction_shiftreg<-mkRegA(0);
+       Reg#(Bit#(5)) instruction<-mkRegA(`IDCODE); // clock this by the inverted clock
+       Reg#(Bit#(1)) bypass_sr<-mkRegA(0);
+       Reg#(Bit#(32)) idcode_sr<-mkRegA(`IDCODEVALUE);
+
+       Wire#(Bool) wr_dmihardreset_generated<-mkDWire(False);
+       Reg#(Bit#(1)) rg_dmihardreset<-mkRegA(0);
+       Reg#(Bit#(1)) dmihardreset=condwriteSideEffect(rg_dmihardreset,wr_dmihardreset_generated._write(True));
+       Wire#(Bool) wr_dmireset_generated<-mkDWire(False);
+       Reg#(Bit#(1)) rg_dmireset<-mkRegA(0);
+       Reg#(Bit#(1)) dmireset=condwriteSideEffect(rg_dmireset,wr_dmireset_generated._write(True));
+       Reg#(Bit#(3)) idle=readOnlyReg(3'd7);
+       Reg#(Bit#(2)) dmistat<-mkRegA(0);
+       Reg#(Bit#(6)) abits =readOnlyReg(6'd6);
+       Reg#(Bit#(4)) version = readOnlyReg('d1);
+       Reg#(Bit#(32)) dtmcontrol=concatReg8(readOnlyReg(14'd0),
+               dmihardreset,dmireset,readOnlyReg(1'd0),
+               idle,dmistat,abits,version);
+       Reg#(Bit#(32)) dtmcontrol_shiftreg<-mkRegA({17'd0,3'd2,2'd0,6'd6,4'd1});
+
+       Reg#(Bit#(40)) dmiaccess_shiftreg[2]<-mkCReg(2,'d0);
+       Reg#(Bit#(2)) response_status<-mkReg(0);
+       Reg#(Bool) rg_dmibusy<-mkRegA(False);
+
+
+   Bit#(1) bypass_sel          = instruction == `BYPASS?1:0;
+   Bit#(1) idcode_sel          = instruction == `IDCODE?1:0;
+   Bit#(1) dbg_sel                     = instruction == `DEBUG?1:0;
+   Bit#(1) dtmcontrol_sel      = instruction == `DTMCONTROL?1:0;
+   Bit#(1) dmi_sel                     = instruction == `DMIACCESS?1:0;
+
+       Bit#(1) instruction_tdo=instruction_shiftreg[0];
+       Bit#(1) bypass_tdo=bypass_sr;
+       Bit#(1) idcode_tdo=idcode_sr[0];
+       Bit#(1) dtmcontrol_tdo=dtmcontrol_shiftreg[0];
+       Bit#(1) dmiaccess_tdo=dmiaccess_shiftreg[0][0];
+
+       Reg#(Bit#(1)) rg_tdo<-mkRegA(0);
+
+       /*== This rule implements the TAPs STATE MACHINE====== */
+       `ifdef verbose
+       rule just_display;
+               $display($time,"\tTAPSTATE: ",fshow(tapstate),"\tINSTRUCTION: %h",instruction_shiftreg, " DMIACCESS: %h",dmiaccess_shiftreg[1]);
+       endrule
+       `endif
+
+       rule reset_tap(wr_trst);
+               tapstate<=TestLogicReset;
+               instruction<=`IDCODE;
+               instruction_shiftreg<=0; 
+               dtmcontrol<=0;
+               rg_dmibusy<=False;
+               dmiaccess_shiftreg[1]<=0;
+               dtmcontrol_shiftreg<=({17'd0,3'd2,2'd0,6'd6,4'd1});
+               idcode_sr<=`IDCODEVALUE;
+               bypass_sr<=0;
+       endrule
+       rule tap_state_machine(posedge_clk && !wr_trst);
+               case(tapstate)
+                       TestLogicReset: if(wr_tms==0) tapstate<=RunTestIdle;
+         RunTestIdle   : if(wr_tms==1) tapstate <= SelectDRScan;
+         SelectDRScan  : if(wr_tms==1) tapstate <= SelectIRScan;
+                         else          tapstate <= CaptureDR;
+         CaptureDR     : if(wr_tms==0) tapstate <= ShiftDR;
+                         else          tapstate <= Exit1DR;
+         ShiftDR       : if(wr_tms==1) tapstate <= Exit1DR;
+         Exit1DR       : if(wr_tms==0) tapstate <= PauseDR;
+                         else          tapstate <= UpdateDR;
+         PauseDR       : if(wr_tms==1) tapstate <= Exit2DR;
+         Exit2DR       : if(wr_tms==1) tapstate <= UpdateDR;
+                         else          tapstate <= ShiftDR;
+         UpdateDR      : if(wr_tms==1) tapstate <= SelectDRScan;
+                         else          tapstate <= RunTestIdle;
+         SelectIRScan  : if(wr_tms==1) tapstate <= TestLogicReset;
+                         else          tapstate <= CaptureIR;
+         CaptureIR     : if(wr_tms==0) tapstate <= ShiftIR;
+                         else          tapstate <= Exit1IR;
+         ShiftIR       : if(wr_tms==1) tapstate <= Exit1IR;
+         Exit1IR       : if(wr_tms==0) tapstate <= PauseIR;
+                         else          tapstate <= UpdateIR;
+         PauseIR       : if(wr_tms==1) tapstate <= Exit2IR;
+         Exit2IR       : if(wr_tms==1) tapstate <= UpdateIR;
+                         else          tapstate <= ShiftIR;
+         UpdateIR      : if(wr_tms==1) tapstate <= SelectDRScan;
+                         else          tapstate <= RunTestIdle;
+         default       :               tapstate <= TestLogicReset;
+               endcase
+       endrule
+
+       rule dmireset_generated(wr_dmireset_generated && !wr_trst);
+               dmiaccess_shiftreg[1][1:0]<='d0;
+               response_status<=0;
+       endrule
+       rule dmihardreset_generated(wr_dmihardreset_generated && !wr_trst);
+               request_to_DM.deq;
+               response_from_DM.deq;
+               rg_dmibusy<=False;
+       endrule
+
+       /*======= perform dtmcontrol shifts ======== */
+       rule shift_dtm(posedge_clk && !wr_trst);
+               case(tapstate)
+                       TestLogicReset: dtmcontrol<={17'd0,idle,2'b0,abits,version};
+                       CaptureDR:      if(dtmcontrol_sel==1) dtmcontrol_shiftreg<=dtmcontrol;
+                       ShiftDR:                if(dtmcontrol_sel==1) dtmcontrol_shiftreg<={wr_tdi,dtmcontrol_shiftreg[31:1]};
+                       UpdateDR:       if(dtmcontrol_sel==1) dtmcontrol<=dtmcontrol_shiftreg;
+               endcase
+       endrule
+       /*========================================== */
+       /*======= perform dmiaccess shifts ======== */
+       rule shift_dmiaccess(posedge_clk && !wr_dmihardreset_generated && !wr_trst && !wr_dmireset_generated);
+               case(tapstate)
+                       TestLogicReset: dmiaccess_shiftreg[0]<='d0;
+                       CaptureDR:      if(dmi_sel==1) 
+                               if(response_from_DM.notEmpty)begin 
+                                       let x=response_from_DM.first[33:0];
+                                       $display($time,"\tDTM: Getting response: data %h op: %h",x[33:2],x[1:0]);
+                                       x[1:0]=x[1:0]|response_status;// keeping the lower 2 bits sticky
+                                       dmiaccess_shiftreg[0][33:0]<=x; 
+                                       response_status<=x[1:0];
+                                       response_from_DM.deq; 
+                                       $display($time,"\tDTM: New DMIACCESS value: %h",x);
+                                       rg_dmibusy<=False;
+                               end
+                       ShiftDR:                if(dmi_sel==1) dmiaccess_shiftreg[0]<={wr_tdi,dmiaccess_shiftreg[0][39:1]};
+                       UpdateDR:       if(dmi_sel==1) 
+                               if(request_to_DM.notFull && dmiaccess_shiftreg[0][1:0]!=0 && rg_dmibusy==False)begin
+                                       request_to_DM.enq(dmiaccess_shiftreg[0]);
+                                       rg_dmibusy<=True;
+                                       $display($time,"\tDTM: Sending request to Debug: %h",dmiaccess_shiftreg[0]);
+                               end
+                               else if(rg_dmibusy) begin
+                                       response_from_DM.enq('d3);
+                               end
+               endcase
+       endrule
+       /*========================================== */
+
+       /*== perform instruction register shifts === */
+       rule shift_reg(posedge_clk && !wr_trst);
+               case(tapstate)
+                       CaptureIR:      instruction_shiftreg<='b10101;
+                       ShiftIR  :      instruction_shiftreg<= {wr_tdi,instruction_shiftreg[4:1]};
+               endcase
+       endrule
+       rule transfer_instruction_on_nedge(negedge_clk && !wr_trst); // TODO negedge here
+               case(tapstate)
+                       TestLogicReset  :instruction<=`IDCODE;
+                       UpdateIR                        :instruction<=instruction_shiftreg;
+               endcase
+       endrule
+
+       /*==== Bypass Section === */
+       rule bypass_logic(posedge_clk && !wr_trst);
+               case(tapstate)
+                       TestLogicReset: bypass_sr<=1'b0;
+                       CaptureDR         : if(bypass_sel==1) bypass_sr<=1'b0;
+                       ShiftDR           : if(bypass_sel==1) bypass_sr<=wr_tdi;
+               endcase
+       endrule
+
+       /*======= IDCODE section === */
+       rule idcode_logic(posedge_clk && !wr_trst);
+               case(tapstate)
+                       TestLogicReset:idcode_sr<=`IDCODEVALUE;
+                       CaptureDR:      if(idcode_sel==1) idcode_sr<=`IDCODEVALUE;
+                       ShiftDR :   if(idcode_sel==1) idcode_sr<={wr_tdi,idcode_sr[31:1]};
+               endcase
+       endrule
+
+       rule generate_tdo_outputpin(negedge_clk && !wr_trst);
+               if(tapstate==ShiftIR)
+                       rg_tdo<=instruction_tdo;
+               else
+                       case(instruction)
+                               `IDCODE: rg_tdo<=idcode_tdo;
+                               `DEBUG : rg_tdo<=wr_debug_tdi;
+                               `EXTEST: rg_tdo<=wr_bs_chain_tdi;
+                               `SAMPLE_PRELOAD: rg_tdo<=wr_bs_chain_tdi;
+                               `BYPASS: rg_tdo<=bypass_tdo;
+                               `DTMCONTROL: rg_tdo<=dtmcontrol_tdo;
+                               `DMIACCESS: rg_tdo<=dmiaccess_tdo;
+                               default:        rg_tdo<=bypass_tdo;
+                       endcase
+       endrule
+
+       /*======== JTAG input pins ===== */
+       method Action tms_i(Bit#(1) tms);
+               wr_tms<=tms;
+       endmethod
+       method Action tdi_i(Bit#(1) tdi);
+               wr_tdi<=tdi;
+       endmethod
+       method Action tck_i(Bit#(1) tck);
+               prv_clk<=tck;
+               if(prv_clk==0 && tck==1)
+                       posedge_clk.send;
+               else if(prv_clk==1 && tck==0)
+                       negedge_clk.send;
+       endmethod
+       method Action trst_i(Bit#(1) trst);
+               wr_trst<=unpack(trst);
+       endmethod
+       /*============================= */
+       method Action debug_tdi_i(Bit#(1) debug_tdi);
+               wr_debug_tdi<=debug_tdi;
+       endmethod
+       method Action bs_chain_i(Bit#(1) bs_chain);
+               wr_bs_chain_tdi<=bs_chain;
+       endmethod
+       /*======== TAP States ============= */
+       method shift_dr=tapstate==ShiftDR?1:0;
+       method pause_dr=tapstate==PauseDR?1:0;
+       method update_dr=tapstate==UpdateDR?1:0;
+       method capture_dr=tapstate==CaptureDR?1:0;
+       /*=================================== */
+       /*=========== Output for BS Chain ==== */
+       method extest_select                            =instruction==`EXTEST?1:0;
+       method sample_preload_select    =instruction==`SAMPLE_PRELOAD?1:0;
+       method debug_select                             =instruction==`DEBUG?1:0;
+       /*================================ */
+       /*======= JTAG Output Pins ====== */
+       method tdo = rg_tdo;
+       method debug_tdo = wr_tdi;
+       method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
+       method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull);
+               response_from_DM.enq(responsedm);
+       endmethod
+       method ActionValue#(Bit#(40)) request_to_dm if(request_to_DM.notEmpty);
+               request_to_DM.deq;
+               return request_to_DM.first;
+       endmethod
+       endmodule
+
+endpackage
diff --git a/src/peripherals/sdram/bsvmksdram_model_wrapper.bsv b/src/peripherals/sdram/bsvmksdram_model_wrapper.bsv
new file mode 100644 (file)
index 0000000..4d31f10
--- /dev/null
@@ -0,0 +1,124 @@
+/*
+Copyright (c) 2013, IIT Madras
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+*  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+*  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+*  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+// Bluespec wrapper, created by Import BVI Wizard
+// Created on: Mon Nov 06 17:30:03 IST 2017
+// Created by: vishvesh
+// Bluespec version: 2017.03.beta1 2017-03-16 35049
+
+
+interface Ifc_sdram_model;
+       interface Inout#(Bit#(32)) dq;
+       (*always_ready*)
+       method Action iAddr (Bit#(11) addr);
+       (*always_ready*)
+       method Action iBa (Bit#(2) ba);
+       (*always_ready*)
+       method Action iCke (bit cke);
+       (*always_ready*)
+       method Action iCs_n (bit cs_n);
+       (*always_ready*)
+       method Action iRas_n (bit ras_n);
+       (*always_ready*)
+       method Action iCas_n (bit cas_n);
+       (*always_ready*)
+       method Action iWe_n (bit we_n);
+       (*always_ready*)
+       method Action iDqm (Bit#(4) dqm);
+endinterface
+
+import "BVI" mt48lc2m32b2 =
+module mksdram_model_wrapper #(String file) (Ifc_sdram_model);
+
+       parameter FILENAME = file;
+       parameter addr_bits = 11;
+       parameter data_bits = 32;
+       parameter col_bits = 8;
+       parameter mem_sizes = 524287;
+       parameter tAC = 5.5;
+       parameter tHZ = 5.5;
+       parameter tOH = 2.5;
+       parameter tMRD = 2.0;
+       parameter tRAS = 42.0;
+       parameter tRC = 60.0;
+       parameter tRCD = 18.0;
+       parameter tRFC = 60.0;
+       parameter tRP = 18.0;
+       parameter tRRD = 12.0;
+       parameter tWRa = 6.0;
+       parameter tWRm = 12.0;
+
+       default_clock clk_old_Clk;
+       default_reset rst;
+
+       input_clock clk_old_Clk (old_Clk)  <- exposeCurrentClock;
+       input_reset rst (/* empty */) clocked_by(clk_old_Clk)  <- exposeCurrentReset;
+
+       ifc_inout dq(Dq) clocked_by (clk_old_Clk) reset_by (rst);
+
+       method iAddr (Addr /*addr_bits-1:0*/)
+                enable((*inhigh*)iAddr_enable) clocked_by(clk_old_Clk) reset_by(rst);
+       method iBa (Ba /*1:0*/)
+                enable((*inhigh*)iBa_enable) clocked_by(clk_old_Clk) reset_by(rst);
+       method iCke (Cke )
+                enable((*inhigh*)iCke_enable) clocked_by(clk_old_Clk) reset_by(rst);
+       method iCs_n (Cs_n )
+                enable((*inhigh*)iCs_n_enable) clocked_by(clk_old_Clk) reset_by(rst);
+       method iRas_n (Ras_n )
+                enable((*inhigh*)iRas_n_enable) clocked_by(clk_old_Clk) reset_by(rst);
+       method iCas_n (Cas_n)
+                enable((*inhigh*)iCas_n_enable) clocked_by(clk_old_Clk) reset_by(rst);
+       method iWe_n (We_n )
+                enable((*inhigh*)iWe_n_enable) clocked_by(clk_old_Clk) reset_by(rst);
+       method iDqm (Dqm /*3:0*/)
+                enable((*inhigh*)iDqm_enable) clocked_by(clk_old_Clk) reset_by(rst);
+
+       schedule iAddr C iAddr;
+       schedule iAddr CF iBa;
+       schedule iAddr CF iCke;
+       schedule iAddr CF iCs_n;
+       schedule iAddr CF iRas_n;
+       schedule iAddr CF iCas_n;
+       schedule iAddr CF iWe_n;
+       schedule iAddr CF iDqm;
+       schedule iBa C iBa;
+       schedule iBa CF iCke;
+       schedule iBa CF iCs_n;
+       schedule iBa CF iRas_n;
+       schedule iBa CF iCas_n;
+       schedule iBa CF iWe_n;
+       schedule iBa CF iDqm;
+       schedule iCke C iCke;
+       schedule iCke CF iCs_n;
+       schedule iCke CF iRas_n;
+       schedule iCke CF iCas_n;
+       schedule iCke CF iWe_n;
+       schedule iCke CF iDqm;
+       schedule iCs_n C iCs_n;
+       schedule iCs_n CF iRas_n;
+       schedule iCs_n CF iCas_n;
+       schedule iCs_n CF iWe_n;
+       schedule iCs_n CF iDqm;
+       schedule iRas_n C iRas_n;
+       schedule iRas_n CF iCas_n;
+       schedule iRas_n CF iWe_n;
+       schedule iRas_n CF iDqm;
+       schedule iCas_n C iCas_n;
+       schedule iCas_n CF iWe_n;
+       schedule iCas_n CF iDqm;
+       schedule iWe_n C iWe_n;
+       schedule iWe_n CF iDqm;
+       schedule iDqm C iDqm;
+endmodule
+
+
diff --git a/src/peripherals/sdram/bsvmksdrc_top.bsv b/src/peripherals/sdram/bsvmksdrc_top.bsv
new file mode 100644 (file)
index 0000000..5ff6a79
--- /dev/null
@@ -0,0 +1,928 @@
+/*
+Copyright (c) 2013, IIT Madras
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+*  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+*  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+*  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+*/
+// Bluespec wrapper, created by Import BVI Wizard
+// Created on: Mon Jul 03 20:03:44 IST 2017
+// Created by: vishvesh
+// Bluespec version: 2017.03.beta1 2017-03-16 35049
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W  3
+
+interface Ifc_sdram;
+    (*always_ready, always_enabled*)
+    method Action iapp_req (bit app_req);
+    (*always_ready, always_enabled*)
+    method Action iapp_req_wrap (bit app_req_wrap);
+    (*always_ready, always_enabled*)
+       method Action icfg_sdr_width (Bit#(2) cfg_sdr_width);
+    (*always_ready, always_enabled*)
+       method Action icfg_colbits (Bit#(2) cfg_colbits);
+    (*always_ready, always_enabled*)
+       method Action icfg_sdr_tras_d (Bit#(4) cfg_sdr_tras_d);
+       (*always_ready, always_enabled*)
+       method Action icfg_sdr_trp_d (Bit#(4) cfg_sdr_trp_d);
+       (*always_ready, always_enabled*)
+       method Action icfg_sdr_trcd_d (Bit#(4) cfg_sdr_trcd_d);
+       (*always_ready, always_enabled*)
+       method Action icfg_sdr_en (bit cfg_sdr_en);
+       (*always_ready, always_enabled*)
+       method Action icfg_req_depth (Bit#(2) cfg_req_depth);
+       (*always_ready, always_enabled*)
+       method Action icfg_sdr_mode_reg (Bit#(13) cfg_sdr_mode_reg);
+       (*always_ready, always_enabled*)
+       method Action icfg_sdr_cas (Bit#(3) cfg_sdr_cas);
+       (*always_ready, always_enabled*)
+       method Action icfg_sdr_trcar_d (Bit#(4) cfg_sdr_trcar_d);
+       (*always_ready, always_enabled*)
+       method Action icfg_sdr_twr_d (Bit#(4) cfg_sdr_twr_d);
+       (*always_ready, always_enabled*)
+    method Action icfg_sdr_rfsh (Bit#(`SDR_RFSH_TIMER_W) cfg_sdr_rfsh);
+       (*always_ready, always_enabled*)
+    method Action icfg_sdr_rfmax (Bit#(`SDR_RFSH_ROW_CNT_W) cfg_sdr_rfmax);
+       (*always_ready, always_enabled*)
+       method Action iapp_req_addr (Bit#(26) app_req_addr);
+       (*always_ready, always_enabled*)
+       method Action iapp_req_len (Bit#(9) app_req_len);
+       (*always_ready, always_enabled*)
+       method Action iapp_req_wr_n (bit app_req_wr_n);
+       (*always_ready, always_enabled*)
+       method Action iapp_wr_en_n (Bit#(8) app_wr_en_n);
+       (*always_ready, always_enabled*)
+       method Action iapp_wr_data (Bit#(64) app_wr_data);
+       (*always_ready, always_enabled*)
+    method Action ipad_sdr_din (Bit#(64) pad_sdr_din);
+       (*always_enabled*)
+       method Bool osdr_cke ();
+       (*always_enabled*)
+       method Bool osdr_cs_n ();
+       (*always_enabled*)
+       method Bool osdr_ras_n ();
+       (*always_enabled*)
+       method Bool osdr_cas_n ();
+       (*always_enabled*)
+       method Bool osdr_we_n ();
+       (*always_enabled*)
+       method Bit#(8) osdr_dqm ();
+       (*always_enabled*)
+       method Bit#(2) osdr_ba ();
+       (*always_enabled*)
+       method Bit#(13) osdr_addr ();
+       (*always_enabled*)
+       method Bit#(64) osdr_dout ();
+       (*always_enabled*)
+       method Bit#(8) osdr_den_n ();
+       (*always_enabled*)
+       method Bool osdr_init_done ();
+       (*always_enabled*)
+       method Bool oapp_req_ack ();
+       (*always_enabled*)
+       method Bool oapp_wr_next_req ();
+       (*always_enabled*)
+       method Bool oapp_rd_valid ();
+       (*always_enabled*)
+       method Bool oapp_last_rd ();
+       (*always_enabled*)
+       method Bool oapp_last_wr ();
+       (*always_enabled*)
+       method Bit#(64) oapp_rd_data ();
+endinterface
+
+import "BVI" sdrc_top =
+module mksdrc_top  (Ifc_sdram);
+
+       parameter APP_AW = 26;
+       parameter APP_DW = 64;
+       parameter APP_BW = 8;
+       parameter APP_RW = 9;
+       parameter SDR_DW = 64;
+       parameter SDR_BW = 8;
+       parameter dw = 64;
+       parameter tw = 8;
+       parameter bl = 9;
+
+       default_clock clk_sdram_clk;
+       default_reset rst_sdram_resetn;
+
+       input_clock clk_sdram_clk (sdram_clk)  <- exposeCurrentClock;
+       input_reset rst_sdram_resetn (sdram_resetn) clocked_by(clk_sdram_clk)  <- exposeCurrentReset;
+
+
+    method ipad_sdr_din (pad_sdr_din)
+        enable((*inhigh*)ipad_sdr_din_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+    method iapp_req (app_req )
+                enable((*inhigh*)iapp_req_enable)  clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+    method iapp_req_wrap (app_req_wrap )
+                enable((*inhigh*)iapp_req_wrap_enable)  clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_width (cfg_sdr_width /*3:0*/)
+                enable((*inhigh*)icfg_sdr_width_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_colbits (cfg_colbits /*3:0*/)
+                enable((*inhigh*)icfg_colbits_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_tras_d (cfg_sdr_tras_d /*3:0*/)
+                enable((*inhigh*)icfg_sdr_tras_d_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_trp_d (cfg_sdr_trp_d /*3:0*/)
+                enable((*inhigh*)icfg_sdr_trp_d_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_trcd_d (cfg_sdr_trcd_d /*3:0*/)
+                enable((*inhigh*)icfg_sdr_trcd_d_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_en (cfg_sdr_en )
+                enable((*inhigh*)icfg_sdr_en_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_req_depth (cfg_req_depth /*1:0*/)
+                enable((*inhigh*)icfg_req_depth_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_mode_reg (cfg_sdr_mode_reg /*12:0*/)
+                enable((*inhigh*)icfg_sdr_mode_reg_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_cas (cfg_sdr_cas /*2:0*/)
+                enable((*inhigh*)icfg_sdr_cas_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_trcar_d (cfg_sdr_trcar_d /*3:0*/)
+                enable((*inhigh*)icfg_sdr_trcar_d_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_twr_d (cfg_sdr_twr_d /*3:0*/)
+                enable((*inhigh*)icfg_sdr_twr_d_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_rfsh (cfg_sdr_rfsh /*`SDR_RFSH_TIMER_W-1:0*/)
+                enable((*inhigh*)icfg_sdr_rfsh_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method icfg_sdr_rfmax (cfg_sdr_rfmax /*`SDR_RFSH_ROW_CNT_W-1:0*/)
+                enable((*inhigh*)icfg_sdr_rfmax_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method iapp_req_addr (app_req_addr /*APP_AW-1:0*/)
+                enable((*inhigh*)iapp_req_addr_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method iapp_req_len (app_req_len /*bl-1:0*/)
+                enable((*inhigh*)iapp_req_len_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method iapp_req_wr_n (app_req_wr_n )
+                enable((*inhigh*)iapp_req_wr_n_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method iapp_wr_en_n (app_wr_en_n /*dw/8-1:0*/)
+                enable((*inhigh*)iapp_wr_en_n_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method iapp_wr_data (app_wr_data /*dw-1:0*/)
+                enable((*inhigh*)iapp_wr_data_enable) clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+
+       method sdr_dout osdr_dout ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_den_n osdr_den_n ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_cke osdr_cke ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_cs_n osdr_cs_n ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_ras_n osdr_ras_n ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_cas_n osdr_cas_n ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_we_n osdr_we_n ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_dqm /* SDR_BW-1 : 0 */ osdr_dqm ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_ba /* 1 : 0 */ osdr_ba ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_addr /* 12 : 0 */ osdr_addr ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method sdr_init_done osdr_init_done ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method app_req_ack oapp_req_ack ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method app_wr_next_req oapp_wr_next_req ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method app_rd_valid oapp_rd_valid ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method app_last_rd oapp_last_rd ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method app_last_wr oapp_last_wr ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+       method app_rd_data /* dw-1 : 0 */ oapp_rd_data ()
+                clocked_by(clk_sdram_clk) reset_by(rst_sdram_resetn);
+
+
+    schedule icfg_colbits C icfg_colbits;
+    schedule icfg_colbits CF icfg_sdr_width;
+    schedule icfg_colbits CF ipad_sdr_din;
+    schedule icfg_colbits CF iapp_req;
+       schedule icfg_colbits CF iapp_req_addr;
+       schedule icfg_colbits CF iapp_req_len;
+       schedule icfg_colbits CF iapp_req_wr_n;
+       schedule icfg_colbits CF iapp_wr_en_n;
+       schedule icfg_colbits CF iapp_wr_data;
+       schedule icfg_colbits CF icfg_sdr_tras_d;
+       schedule icfg_colbits CF icfg_sdr_trp_d;
+       schedule icfg_colbits CF icfg_sdr_trcd_d;
+       schedule icfg_colbits CF icfg_sdr_en;
+       schedule icfg_colbits CF icfg_req_depth;
+       schedule icfg_colbits CF icfg_sdr_mode_reg;
+       schedule icfg_colbits CF icfg_sdr_cas;
+       schedule icfg_colbits CF icfg_sdr_trcar_d;
+       schedule icfg_colbits CF icfg_sdr_twr_d;
+       schedule icfg_colbits CF icfg_sdr_rfmax;
+       schedule icfg_colbits CF icfg_sdr_rfsh;
+       schedule icfg_colbits CF iapp_req_wrap;
+       schedule osdr_cke CF icfg_colbits;
+       schedule osdr_cs_n CF icfg_colbits;
+       schedule osdr_ras_n CF icfg_colbits;
+       schedule osdr_cas_n CF icfg_colbits;
+       schedule osdr_we_n CF icfg_colbits;
+       schedule osdr_dqm CF icfg_colbits;
+       schedule osdr_ba CF icfg_colbits;
+       schedule osdr_addr CF icfg_colbits;
+       schedule osdr_init_done CF icfg_colbits;
+       schedule oapp_req_ack CF icfg_colbits;
+       schedule oapp_wr_next_req CF icfg_colbits;
+       schedule oapp_rd_valid CF icfg_colbits;
+       schedule oapp_last_rd CF icfg_colbits;
+       schedule oapp_last_wr CF icfg_colbits;
+       schedule oapp_rd_data CF icfg_colbits;
+
+
+
+    schedule icfg_sdr_width C icfg_sdr_width;
+    schedule icfg_sdr_width CF ipad_sdr_din;
+    schedule icfg_sdr_width CF iapp_req;
+       schedule icfg_sdr_width CF iapp_req_addr;
+       schedule icfg_sdr_width CF iapp_req_len;
+       schedule icfg_sdr_width CF iapp_req_wr_n;
+       schedule icfg_sdr_width CF iapp_wr_en_n;
+       schedule icfg_sdr_width CF iapp_wr_data;
+       schedule icfg_sdr_width CF icfg_sdr_tras_d;
+       schedule icfg_sdr_width CF icfg_sdr_trp_d;
+       schedule icfg_sdr_width CF icfg_sdr_trcd_d;
+       schedule icfg_sdr_width CF icfg_sdr_en;
+       schedule icfg_sdr_width CF icfg_req_depth;
+       schedule icfg_sdr_width CF icfg_sdr_mode_reg;
+       schedule icfg_sdr_width CF icfg_sdr_cas;
+       schedule icfg_sdr_width CF icfg_sdr_trcar_d;
+       schedule icfg_sdr_width CF icfg_sdr_twr_d;
+       schedule icfg_sdr_width CF icfg_sdr_rfmax;
+       schedule icfg_sdr_width CF icfg_sdr_rfsh;
+       schedule icfg_sdr_width CF iapp_req_wrap;
+       schedule osdr_cke CF icfg_sdr_width;
+       schedule osdr_cs_n CF icfg_sdr_width;
+       schedule osdr_ras_n CF icfg_sdr_width;
+       schedule osdr_cas_n CF icfg_sdr_width;
+       schedule osdr_we_n CF icfg_sdr_width;
+       schedule osdr_dqm CF icfg_sdr_width;
+       schedule osdr_ba CF icfg_sdr_width;
+       schedule osdr_addr CF icfg_sdr_width;
+       schedule osdr_init_done CF icfg_sdr_width;
+       schedule oapp_req_ack CF icfg_sdr_width;
+       schedule oapp_wr_next_req CF icfg_sdr_width;
+       schedule oapp_rd_valid CF icfg_sdr_width;
+       schedule oapp_last_rd CF icfg_sdr_width;
+       schedule oapp_last_wr CF icfg_sdr_width;
+       schedule oapp_rd_data CF icfg_sdr_width;
+    
+    schedule ipad_sdr_din C ipad_sdr_din;
+    schedule ipad_sdr_din CF iapp_req;
+       schedule ipad_sdr_din CF iapp_req_addr;
+       schedule ipad_sdr_din CF iapp_req_len;
+       schedule ipad_sdr_din CF iapp_req_wr_n;
+       schedule ipad_sdr_din CF iapp_wr_en_n;
+       schedule ipad_sdr_din CF iapp_wr_data;
+       schedule ipad_sdr_din CF icfg_sdr_tras_d;
+       schedule ipad_sdr_din CF icfg_sdr_trp_d;
+       schedule ipad_sdr_din CF icfg_sdr_trcd_d;
+       schedule ipad_sdr_din CF icfg_sdr_en;
+       schedule ipad_sdr_din CF icfg_req_depth;
+       schedule ipad_sdr_din CF icfg_sdr_mode_reg;
+       schedule ipad_sdr_din CF icfg_sdr_cas;
+       schedule ipad_sdr_din CF icfg_sdr_trcar_d;
+       schedule ipad_sdr_din CF icfg_sdr_twr_d;
+       schedule ipad_sdr_din CF icfg_sdr_rfmax;
+       schedule ipad_sdr_din CF icfg_sdr_rfsh;
+       schedule ipad_sdr_din CF iapp_req_wrap;
+       schedule osdr_cke CF ipad_sdr_din;
+       schedule osdr_cs_n CF ipad_sdr_din;
+       schedule osdr_ras_n CF ipad_sdr_din;
+       schedule osdr_cas_n CF ipad_sdr_din;
+       schedule osdr_we_n CF ipad_sdr_din;
+       schedule osdr_dqm CF ipad_sdr_din;
+       schedule osdr_ba CF ipad_sdr_din;
+       schedule osdr_addr CF ipad_sdr_din;
+       schedule osdr_init_done CF ipad_sdr_din;
+       schedule oapp_req_ack CF ipad_sdr_din;
+       schedule oapp_wr_next_req CF ipad_sdr_din;
+       schedule oapp_rd_valid CF ipad_sdr_din;
+       schedule oapp_last_rd CF ipad_sdr_din;
+       schedule oapp_last_wr CF ipad_sdr_din;
+       schedule oapp_rd_data CF ipad_sdr_din;
+
+    schedule iapp_req_wrap C iapp_req_wrap;
+    schedule iapp_req_wrap CF iapp_req;
+       schedule iapp_req_wrap CF iapp_req_addr;
+       schedule iapp_req_wrap CF iapp_req_len;
+       schedule iapp_req_wrap CF iapp_req_wr_n;
+       schedule iapp_req_wrap CF iapp_wr_en_n;
+       schedule iapp_req_wrap CF iapp_wr_data;
+       schedule iapp_req_wrap CF icfg_sdr_tras_d;
+       schedule iapp_req_wrap CF icfg_sdr_trp_d;
+       schedule iapp_req_wrap CF icfg_sdr_trcd_d;
+       schedule iapp_req_wrap CF icfg_sdr_en;
+       schedule iapp_req_wrap CF icfg_req_depth;
+       schedule iapp_req_wrap CF icfg_sdr_mode_reg;
+       schedule iapp_req_wrap CF icfg_sdr_cas;
+       schedule iapp_req_wrap CF icfg_sdr_trcar_d;
+       schedule iapp_req_wrap CF icfg_sdr_twr_d;
+       schedule iapp_req_wrap CF icfg_sdr_rfmax;
+       schedule iapp_req_wrap CF icfg_sdr_rfsh;
+       schedule osdr_cke CF iapp_req_wrap;
+       schedule osdr_cs_n CF iapp_req_wrap;
+       schedule osdr_ras_n CF iapp_req_wrap;
+       schedule osdr_cas_n CF iapp_req_wrap;
+       schedule osdr_we_n CF iapp_req_wrap;
+       schedule osdr_dqm CF iapp_req_wrap;
+       schedule osdr_ba CF iapp_req_wrap;
+       schedule osdr_addr CF iapp_req_wrap;
+       schedule osdr_init_done CF iapp_req_wrap;
+       schedule oapp_req_ack CF iapp_req_wrap;
+       schedule oapp_wr_next_req CF iapp_req_wrap;
+       schedule oapp_rd_valid CF iapp_req_wrap;
+       schedule oapp_last_rd CF iapp_req_wrap;
+       schedule oapp_last_wr CF iapp_req_wrap;
+       schedule oapp_rd_data CF iapp_req_wrap;
+    schedule osdr_dout CF iapp_req_wrap;
+    schedule osdr_den_n CF iapp_req_wrap; 
+     
+    schedule iapp_req C iapp_req;
+       schedule iapp_req CF iapp_req_addr;
+       schedule iapp_req CF iapp_req_len;
+       schedule iapp_req CF iapp_req_wr_n;
+       schedule iapp_req CF iapp_wr_en_n;
+       schedule iapp_req CF iapp_wr_data;
+       schedule iapp_req CF icfg_sdr_tras_d;
+       schedule iapp_req CF icfg_sdr_trp_d;
+       schedule iapp_req CF icfg_sdr_trcd_d;
+       schedule iapp_req CF icfg_sdr_en;
+       schedule iapp_req CF icfg_req_depth;
+       schedule iapp_req CF icfg_sdr_mode_reg;
+       schedule iapp_req CF icfg_sdr_cas;
+       schedule iapp_req CF icfg_sdr_trcar_d;
+       schedule iapp_req CF icfg_sdr_twr_d;
+       schedule iapp_req CF icfg_sdr_rfmax;
+       schedule iapp_req CF icfg_sdr_rfsh;
+       schedule osdr_cke CF iapp_req;
+       schedule osdr_cs_n CF iapp_req;
+       schedule osdr_ras_n CF iapp_req;
+       schedule osdr_cas_n CF iapp_req;
+       schedule osdr_we_n CF iapp_req;
+       schedule osdr_dqm CF iapp_req;
+       schedule osdr_ba CF iapp_req;
+       schedule osdr_addr CF iapp_req;
+       schedule osdr_init_done CF iapp_req;
+       schedule oapp_req_ack CF iapp_req;
+       schedule oapp_wr_next_req CF iapp_req;
+       schedule oapp_rd_valid CF iapp_req;
+       schedule oapp_last_rd CF iapp_req;
+       schedule oapp_last_wr CF iapp_req;
+       schedule oapp_rd_data CF iapp_req;
+    schedule osdr_dout CF iapp_req;
+    schedule osdr_den_n CF iapp_req;
+
+    schedule icfg_sdr_tras_d C icfg_sdr_tras_d;
+       schedule icfg_sdr_tras_d CF icfg_sdr_trp_d;
+       schedule icfg_sdr_tras_d CF icfg_sdr_trcd_d;
+       schedule icfg_sdr_tras_d CF icfg_sdr_en;
+       schedule icfg_sdr_tras_d CF icfg_req_depth;
+       schedule icfg_sdr_tras_d CF icfg_sdr_mode_reg;
+       schedule icfg_sdr_tras_d CF icfg_sdr_cas;
+       schedule icfg_sdr_tras_d CF icfg_sdr_trcar_d;
+       schedule icfg_sdr_tras_d CF icfg_sdr_twr_d;
+       schedule icfg_sdr_tras_d CF icfg_sdr_rfsh;
+       schedule icfg_sdr_tras_d CF icfg_sdr_rfmax;
+       schedule icfg_sdr_tras_d CF iapp_req_addr;
+       schedule icfg_sdr_tras_d CF iapp_req_len;
+       schedule icfg_sdr_tras_d CF iapp_req_wr_n;
+       schedule icfg_sdr_tras_d CF iapp_wr_en_n;
+       schedule icfg_sdr_tras_d CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_tras_d;
+       schedule osdr_cs_n CF icfg_sdr_tras_d;
+       schedule osdr_ras_n CF icfg_sdr_tras_d;
+       schedule osdr_cas_n CF icfg_sdr_tras_d;
+       schedule osdr_we_n CF icfg_sdr_tras_d;
+       schedule osdr_dqm CF icfg_sdr_tras_d;
+       schedule osdr_ba CF icfg_sdr_tras_d;
+       schedule osdr_addr CF icfg_sdr_tras_d;
+       schedule osdr_init_done CF icfg_sdr_tras_d;
+       schedule oapp_req_ack CF icfg_sdr_tras_d;
+       schedule oapp_wr_next_req CF icfg_sdr_tras_d;
+       schedule oapp_rd_valid CF icfg_sdr_tras_d;
+       schedule oapp_last_rd CF icfg_sdr_tras_d;
+       schedule oapp_last_wr CF icfg_sdr_tras_d;
+       schedule oapp_rd_data CF icfg_sdr_tras_d;
+    schedule osdr_dout CF icfg_sdr_tras_d;
+    schedule osdr_den_n CF icfg_sdr_tras_d;
+
+
+    schedule icfg_sdr_trp_d C icfg_sdr_trp_d;
+       schedule icfg_sdr_trp_d CF icfg_sdr_trcd_d;
+       schedule icfg_sdr_trp_d CF icfg_sdr_en;
+       schedule icfg_sdr_trp_d CF icfg_req_depth;
+       schedule icfg_sdr_trp_d CF icfg_sdr_mode_reg;
+       schedule icfg_sdr_trp_d CF icfg_sdr_cas;
+       schedule icfg_sdr_trp_d CF icfg_sdr_trcar_d;
+       schedule icfg_sdr_trp_d CF icfg_sdr_twr_d;
+       schedule icfg_sdr_trp_d CF icfg_sdr_rfsh;
+       schedule icfg_sdr_trp_d CF icfg_sdr_rfmax;
+       schedule icfg_sdr_trp_d CF iapp_req_addr;
+       schedule icfg_sdr_trp_d CF iapp_req_len;
+       schedule icfg_sdr_trp_d CF iapp_req_wr_n;
+       schedule icfg_sdr_trp_d CF iapp_wr_en_n;
+       schedule icfg_sdr_trp_d CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_trp_d;
+       schedule osdr_cs_n CF icfg_sdr_trp_d;
+       schedule osdr_ras_n CF icfg_sdr_trp_d;
+       schedule osdr_cas_n CF icfg_sdr_trp_d;
+       schedule osdr_we_n CF icfg_sdr_trp_d;
+       schedule osdr_dqm CF icfg_sdr_trp_d;
+       schedule osdr_ba CF icfg_sdr_trp_d;
+       schedule osdr_addr CF icfg_sdr_trp_d;
+       schedule osdr_init_done CF icfg_sdr_trp_d;
+       schedule oapp_req_ack CF icfg_sdr_trp_d;
+       schedule oapp_wr_next_req CF icfg_sdr_trp_d;
+       schedule oapp_rd_valid CF icfg_sdr_trp_d;
+       schedule oapp_last_rd CF icfg_sdr_trp_d;
+       schedule oapp_last_wr CF icfg_sdr_trp_d;
+       schedule oapp_rd_data CF icfg_sdr_trp_d;
+    schedule osdr_dout CF icfg_sdr_trp_d;
+    schedule osdr_den_n CF icfg_sdr_trp_d;
+
+
+
+    schedule icfg_sdr_trcd_d C icfg_sdr_trcd_d;
+       schedule icfg_sdr_trcd_d CF icfg_sdr_en;
+       schedule icfg_sdr_trcd_d CF icfg_req_depth;
+       schedule icfg_sdr_trcd_d CF icfg_sdr_mode_reg;
+       schedule icfg_sdr_trcd_d CF icfg_sdr_cas;
+       schedule icfg_sdr_trcd_d CF icfg_sdr_trcar_d;
+       schedule icfg_sdr_trcd_d CF icfg_sdr_twr_d;
+       schedule icfg_sdr_trcd_d CF icfg_sdr_rfsh;
+       schedule icfg_sdr_trcd_d CF icfg_sdr_rfmax;
+       schedule icfg_sdr_trcd_d CF iapp_req_addr;
+       schedule icfg_sdr_trcd_d CF iapp_req_len;
+       schedule icfg_sdr_trcd_d CF iapp_req_wr_n;
+       schedule icfg_sdr_trcd_d CF iapp_wr_en_n;
+       schedule icfg_sdr_trcd_d CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_trcd_d;
+       schedule osdr_cs_n CF icfg_sdr_trcd_d;
+       schedule osdr_ras_n CF icfg_sdr_trcd_d;
+       schedule osdr_cas_n CF icfg_sdr_trcd_d;
+       schedule osdr_we_n CF icfg_sdr_trcd_d;
+       schedule osdr_dqm CF icfg_sdr_trcd_d;
+       schedule osdr_ba CF icfg_sdr_trcd_d;
+       schedule osdr_addr CF icfg_sdr_trcd_d;
+       schedule osdr_init_done CF icfg_sdr_trcd_d;
+       schedule oapp_req_ack CF icfg_sdr_trcd_d;
+       schedule oapp_wr_next_req CF icfg_sdr_trcd_d;
+       schedule oapp_rd_valid CF icfg_sdr_trcd_d;
+       schedule oapp_last_rd CF icfg_sdr_trcd_d;
+       schedule oapp_last_wr CF icfg_sdr_trcd_d;
+       schedule oapp_rd_data CF icfg_sdr_trcd_d;
+    schedule osdr_dout CF icfg_sdr_trcd_d;
+    schedule osdr_den_n CF icfg_sdr_trcd_d;
+
+    schedule icfg_sdr_en C icfg_sdr_en;
+       schedule icfg_sdr_en CF icfg_req_depth;
+       schedule icfg_sdr_en CF icfg_sdr_mode_reg;
+       schedule icfg_sdr_en CF icfg_sdr_cas;
+       schedule icfg_sdr_en CF icfg_sdr_trcar_d;
+       schedule icfg_sdr_en CF icfg_sdr_twr_d;
+       schedule icfg_sdr_en CF icfg_sdr_rfsh;
+       schedule icfg_sdr_en CF icfg_sdr_rfmax;
+       schedule icfg_sdr_en CF iapp_req_addr;
+       schedule icfg_sdr_en CF iapp_req_len;
+       schedule icfg_sdr_en CF iapp_req_wr_n;
+       schedule icfg_sdr_en CF iapp_wr_en_n;
+       schedule icfg_sdr_en CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_en;
+       schedule osdr_cs_n CF icfg_sdr_en;
+       schedule osdr_ras_n CF icfg_sdr_en;
+       schedule osdr_cas_n CF icfg_sdr_en;
+       schedule osdr_we_n CF icfg_sdr_en;
+       schedule osdr_dqm CF icfg_sdr_en;
+       schedule osdr_ba CF icfg_sdr_en;
+       schedule osdr_addr CF icfg_sdr_en;
+       schedule osdr_init_done CF icfg_sdr_en;
+       schedule oapp_req_ack CF icfg_sdr_en;
+       schedule oapp_wr_next_req CF icfg_sdr_en;
+       schedule oapp_rd_valid CF icfg_sdr_en;
+       schedule oapp_last_rd CF icfg_sdr_en;
+       schedule oapp_last_wr CF icfg_sdr_en;
+       schedule oapp_rd_data CF icfg_sdr_en;
+    schedule osdr_dout CF icfg_sdr_en;
+    schedule osdr_den_n CF icfg_sdr_en;
+
+    schedule icfg_req_depth C icfg_req_depth;
+       schedule icfg_req_depth CF icfg_sdr_mode_reg;
+       schedule icfg_req_depth CF icfg_sdr_cas;
+       schedule icfg_req_depth CF icfg_sdr_trcar_d;
+       schedule icfg_req_depth CF icfg_sdr_twr_d;
+       schedule icfg_req_depth CF icfg_sdr_rfsh;
+       schedule icfg_req_depth CF icfg_sdr_rfmax;
+       schedule icfg_req_depth CF iapp_req_addr;
+       schedule icfg_req_depth CF iapp_req_len;
+       schedule icfg_req_depth CF iapp_req_wr_n;
+       schedule icfg_req_depth CF iapp_wr_en_n;
+       schedule icfg_req_depth CF iapp_wr_data;
+       schedule osdr_cke CF icfg_req_depth;
+       schedule osdr_cs_n CF icfg_req_depth;
+       schedule osdr_ras_n CF icfg_req_depth;
+       schedule osdr_cas_n CF icfg_req_depth;
+       schedule osdr_we_n CF icfg_req_depth;
+       schedule osdr_dqm CF icfg_req_depth;
+       schedule osdr_ba CF icfg_req_depth;
+       schedule osdr_addr CF icfg_req_depth;
+       schedule osdr_init_done CF icfg_req_depth;
+       schedule oapp_req_ack CF icfg_req_depth;
+       schedule oapp_wr_next_req CF icfg_req_depth;
+       schedule oapp_rd_valid CF icfg_req_depth;
+       schedule oapp_last_rd CF icfg_req_depth;
+       schedule oapp_last_wr CF icfg_req_depth;
+       schedule oapp_rd_data CF icfg_req_depth;
+    schedule osdr_dout CF icfg_req_depth;
+    schedule osdr_den_n CF icfg_req_depth;
+
+    schedule icfg_sdr_mode_reg C icfg_sdr_mode_reg;
+       schedule icfg_sdr_mode_reg CF icfg_sdr_cas;
+       schedule icfg_sdr_mode_reg CF icfg_sdr_trcar_d;
+       schedule icfg_sdr_mode_reg CF icfg_sdr_twr_d;
+       schedule icfg_sdr_mode_reg CF icfg_sdr_rfsh;
+       schedule icfg_sdr_mode_reg CF icfg_sdr_rfmax;
+       schedule icfg_sdr_mode_reg CF iapp_req_addr;
+       schedule icfg_sdr_mode_reg CF iapp_req_len;
+       schedule icfg_sdr_mode_reg CF iapp_req_wr_n;
+       schedule icfg_sdr_mode_reg CF iapp_wr_en_n;
+       schedule icfg_sdr_mode_reg CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_mode_reg;
+       schedule osdr_cs_n CF icfg_sdr_mode_reg;
+       schedule osdr_ras_n CF icfg_sdr_mode_reg;
+       schedule osdr_cas_n CF icfg_sdr_mode_reg;
+       schedule osdr_we_n CF icfg_sdr_mode_reg;
+       schedule osdr_dqm CF icfg_sdr_mode_reg;
+       schedule osdr_ba CF icfg_sdr_mode_reg;
+       schedule osdr_addr CF icfg_sdr_mode_reg;
+       schedule osdr_init_done CF icfg_sdr_mode_reg;
+       schedule oapp_req_ack CF icfg_sdr_mode_reg;
+       schedule oapp_wr_next_req CF icfg_sdr_mode_reg;
+       schedule oapp_rd_valid CF icfg_sdr_mode_reg;
+       schedule oapp_last_rd CF icfg_sdr_mode_reg;
+       schedule oapp_last_wr CF icfg_sdr_mode_reg;
+       schedule oapp_rd_data CF icfg_sdr_mode_reg;
+    schedule osdr_dout CF icfg_sdr_mode_reg;
+    schedule osdr_den_n CF icfg_sdr_mode_reg;
+
+    schedule icfg_sdr_cas C icfg_sdr_cas;
+       schedule icfg_sdr_cas CF icfg_sdr_trcar_d;
+       schedule icfg_sdr_cas CF icfg_sdr_twr_d;
+       schedule icfg_sdr_cas CF icfg_sdr_rfsh;
+       schedule icfg_sdr_cas CF icfg_sdr_rfmax;
+       schedule icfg_sdr_cas CF iapp_req_addr;
+       schedule icfg_sdr_cas CF iapp_req_len;
+       schedule icfg_sdr_cas CF iapp_req_wr_n;
+       schedule icfg_sdr_cas CF iapp_wr_en_n;
+       schedule icfg_sdr_cas CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_cas;
+       schedule osdr_cs_n CF icfg_sdr_cas;
+       schedule osdr_ras_n CF icfg_sdr_cas;
+       schedule osdr_cas_n CF icfg_sdr_cas;
+       schedule osdr_we_n CF icfg_sdr_cas;
+       schedule osdr_dqm CF icfg_sdr_cas;
+       schedule osdr_ba CF icfg_sdr_cas;
+       schedule osdr_addr CF icfg_sdr_cas;
+       schedule osdr_init_done CF icfg_sdr_cas;
+       schedule oapp_req_ack CF icfg_sdr_cas;
+       schedule oapp_wr_next_req CF icfg_sdr_cas;
+       schedule oapp_rd_valid CF icfg_sdr_cas;
+       schedule oapp_last_rd CF icfg_sdr_cas;
+       schedule oapp_last_wr CF icfg_sdr_cas;
+       schedule oapp_rd_data CF icfg_sdr_cas;
+    schedule osdr_dout CF icfg_sdr_cas;
+    schedule osdr_den_n CF icfg_sdr_cas;
+
+    schedule icfg_sdr_trcar_d C icfg_sdr_trcar_d;
+       schedule icfg_sdr_trcar_d CF icfg_sdr_twr_d;
+       schedule icfg_sdr_trcar_d CF icfg_sdr_rfsh;
+       schedule icfg_sdr_trcar_d CF icfg_sdr_rfmax;
+       schedule icfg_sdr_trcar_d CF iapp_req_addr;
+       schedule icfg_sdr_trcar_d CF iapp_req_len;
+       schedule icfg_sdr_trcar_d CF iapp_req_wr_n;
+       schedule icfg_sdr_trcar_d CF iapp_wr_en_n;
+       schedule icfg_sdr_trcar_d CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_trcar_d;
+       schedule osdr_cs_n CF icfg_sdr_trcar_d;
+       schedule osdr_ras_n CF icfg_sdr_trcar_d;
+       schedule osdr_cas_n CF icfg_sdr_trcar_d;
+       schedule osdr_we_n CF icfg_sdr_trcar_d;
+       schedule osdr_dqm CF icfg_sdr_trcar_d;
+       schedule osdr_ba CF icfg_sdr_trcar_d;
+       schedule osdr_addr CF icfg_sdr_trcar_d;
+       schedule osdr_init_done CF icfg_sdr_trcar_d;
+       schedule oapp_req_ack CF icfg_sdr_trcar_d;
+       schedule oapp_wr_next_req CF icfg_sdr_trcar_d;
+       schedule oapp_rd_valid CF icfg_sdr_trcar_d;
+       schedule oapp_last_rd CF icfg_sdr_trcar_d;
+       schedule oapp_last_wr CF icfg_sdr_trcar_d;
+       schedule oapp_rd_data CF icfg_sdr_trcar_d;
+    schedule osdr_dout CF icfg_sdr_trcar_d;
+    schedule osdr_den_n CF icfg_sdr_trcar_d;
+
+    schedule icfg_sdr_twr_d C icfg_sdr_twr_d;
+       schedule icfg_sdr_twr_d CF icfg_sdr_rfsh;
+       schedule icfg_sdr_twr_d CF icfg_sdr_rfmax;
+       schedule icfg_sdr_twr_d CF iapp_req_addr;
+       schedule icfg_sdr_twr_d CF iapp_req_len;
+       schedule icfg_sdr_twr_d CF iapp_req_wr_n;
+       schedule icfg_sdr_twr_d CF iapp_wr_en_n;
+       schedule icfg_sdr_twr_d CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_twr_d;
+       schedule osdr_cs_n CF icfg_sdr_twr_d;
+       schedule osdr_ras_n CF icfg_sdr_twr_d;
+       schedule osdr_cas_n CF icfg_sdr_twr_d;
+       schedule osdr_we_n CF icfg_sdr_twr_d;
+       schedule osdr_dqm CF icfg_sdr_twr_d;
+       schedule osdr_ba CF icfg_sdr_twr_d;
+       schedule osdr_addr CF icfg_sdr_twr_d;
+       schedule osdr_init_done CF icfg_sdr_twr_d;
+       schedule oapp_req_ack CF icfg_sdr_twr_d;
+       schedule oapp_wr_next_req CF icfg_sdr_twr_d;
+       schedule oapp_rd_valid CF icfg_sdr_twr_d;
+       schedule oapp_last_rd CF icfg_sdr_twr_d;
+       schedule oapp_last_wr CF icfg_sdr_twr_d;
+       schedule oapp_rd_data CF icfg_sdr_twr_d;
+    schedule osdr_dout CF icfg_sdr_twr_d;
+    schedule osdr_den_n CF icfg_sdr_twr_d;
+
+    schedule icfg_sdr_rfsh C icfg_sdr_rfsh;
+       schedule icfg_sdr_rfsh CF icfg_sdr_rfmax;
+       schedule icfg_sdr_rfsh CF iapp_req_addr;
+       schedule icfg_sdr_rfsh CF iapp_req_len;
+       schedule icfg_sdr_rfsh CF iapp_req_wr_n;
+       schedule icfg_sdr_rfsh CF iapp_wr_en_n;
+       schedule icfg_sdr_rfsh CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_rfsh;
+       schedule osdr_cs_n CF icfg_sdr_rfsh;
+       schedule osdr_ras_n CF icfg_sdr_rfsh;
+       schedule osdr_cas_n CF icfg_sdr_rfsh;
+       schedule osdr_we_n CF icfg_sdr_rfsh;
+       schedule osdr_dqm CF icfg_sdr_rfsh;
+       schedule osdr_ba CF icfg_sdr_rfsh;
+       schedule osdr_addr CF icfg_sdr_rfsh;
+       schedule osdr_init_done CF icfg_sdr_rfsh;
+       schedule oapp_req_ack CF icfg_sdr_rfsh;
+       schedule oapp_wr_next_req CF icfg_sdr_rfsh;
+       schedule oapp_rd_valid CF icfg_sdr_rfsh;
+       schedule oapp_last_rd CF icfg_sdr_rfsh;
+       schedule oapp_last_wr CF icfg_sdr_rfsh;
+       schedule oapp_rd_data CF icfg_sdr_rfsh;
+    schedule osdr_dout CF icfg_sdr_rfsh;
+    schedule osdr_den_n CF icfg_sdr_rfsh;
+
+    schedule icfg_sdr_rfmax C icfg_sdr_rfmax;
+       schedule icfg_sdr_rfmax CF iapp_req_addr;
+       schedule icfg_sdr_rfmax CF iapp_req_len;
+       schedule icfg_sdr_rfmax CF iapp_req_wr_n;
+       schedule icfg_sdr_rfmax CF iapp_wr_en_n;
+       schedule icfg_sdr_rfmax CF iapp_wr_data;
+       schedule osdr_cke CF icfg_sdr_rfmax;
+       schedule osdr_cs_n CF icfg_sdr_rfmax;
+       schedule osdr_ras_n CF icfg_sdr_rfmax;
+       schedule osdr_cas_n CF icfg_sdr_rfmax;
+       schedule osdr_we_n CF icfg_sdr_rfmax;
+       schedule osdr_dqm CF icfg_sdr_rfmax;
+       schedule osdr_ba CF icfg_sdr_rfmax;
+       schedule osdr_addr CF icfg_sdr_rfmax;
+       schedule osdr_init_done CF icfg_sdr_rfmax;
+       schedule oapp_req_ack CF icfg_sdr_rfmax;
+       schedule oapp_wr_next_req CF icfg_sdr_rfmax;
+       schedule oapp_rd_valid CF icfg_sdr_rfmax;
+       schedule oapp_last_rd CF icfg_sdr_rfmax;
+       schedule oapp_last_wr CF icfg_sdr_rfmax;
+       schedule oapp_rd_data CF icfg_sdr_rfmax;
+    schedule osdr_dout CF icfg_sdr_rfmax;
+    schedule osdr_den_n CF icfg_sdr_rfmax;
+
+    schedule iapp_req_addr C iapp_req_addr;
+       schedule iapp_req_addr CF iapp_req_len;
+       schedule iapp_req_addr CF iapp_req_wr_n;
+       schedule iapp_req_addr CF iapp_wr_en_n;
+       schedule iapp_req_addr CF iapp_wr_data;
+       schedule osdr_cke CF iapp_req_addr;
+       schedule osdr_cs_n CF iapp_req_addr;
+       schedule osdr_ras_n CF iapp_req_addr;
+       schedule osdr_cas_n CF iapp_req_addr;
+       schedule osdr_we_n CF iapp_req_addr;
+       schedule osdr_dqm CF iapp_req_addr;
+       schedule osdr_ba CF iapp_req_addr;
+       schedule osdr_addr CF iapp_req_addr;
+       schedule osdr_init_done CF iapp_req_addr;
+       schedule oapp_req_ack CF iapp_req_addr;
+       schedule oapp_wr_next_req CF iapp_req_addr;
+       schedule oapp_rd_valid CF iapp_req_addr;
+       schedule oapp_last_rd CF iapp_req_addr;
+       schedule oapp_last_wr CF iapp_req_addr;
+       schedule oapp_rd_data CF iapp_req_addr;
+    schedule osdr_dout CF iapp_req_addr;
+    schedule osdr_den_n CF iapp_req_addr;
+
+    schedule iapp_req_len C iapp_req_len;
+       schedule iapp_req_len CF iapp_req_wr_n;
+       schedule iapp_req_len CF iapp_wr_en_n;
+       schedule iapp_req_len CF iapp_wr_data;
+       schedule osdr_cke CF iapp_req_len;
+       schedule osdr_cs_n CF iapp_req_len;
+       schedule osdr_ras_n CF iapp_req_len;
+       schedule osdr_cas_n CF iapp_req_len;
+       schedule osdr_we_n CF iapp_req_len;
+       schedule osdr_dqm CF iapp_req_len;
+       schedule osdr_ba CF iapp_req_len;
+       schedule osdr_addr CF iapp_req_len;
+       schedule osdr_init_done CF iapp_req_len;
+       schedule oapp_req_ack CF iapp_req_len;
+       schedule oapp_wr_next_req CF iapp_req_len;
+       schedule oapp_rd_valid CF iapp_req_len;
+       schedule oapp_last_rd CF iapp_req_len;
+       schedule oapp_last_wr CF iapp_req_len;
+       schedule oapp_rd_data CF iapp_req_len;
+    schedule osdr_dout CF iapp_req_len;
+    schedule osdr_den_n CF iapp_req_len;
+
+    schedule iapp_req_wr_n C iapp_req_wr_n;
+       schedule iapp_req_wr_n CF iapp_wr_en_n;
+       schedule iapp_req_wr_n CF iapp_wr_data;
+       schedule osdr_cke CF iapp_req_wr_n;
+       schedule osdr_cs_n CF iapp_req_wr_n;
+       schedule osdr_ras_n CF iapp_req_wr_n;
+       schedule osdr_cas_n CF iapp_req_wr_n;
+       schedule osdr_we_n CF iapp_req_wr_n;
+       schedule osdr_dqm CF iapp_req_wr_n;
+       schedule osdr_ba CF iapp_req_wr_n;
+       schedule osdr_addr CF iapp_req_wr_n;
+       schedule osdr_init_done CF iapp_req_wr_n;
+       schedule oapp_req_ack CF iapp_req_wr_n;
+       schedule oapp_wr_next_req CF iapp_req_wr_n;
+       schedule oapp_rd_valid CF iapp_req_wr_n;
+       schedule oapp_last_rd CF iapp_req_wr_n;
+       schedule oapp_last_wr CF iapp_req_wr_n;
+       schedule oapp_rd_data CF iapp_req_wr_n;
+    schedule osdr_dout CF iapp_req_wr_n;
+    schedule osdr_den_n CF iapp_req_wr_n;
+
+    schedule iapp_wr_en_n C iapp_wr_en_n;
+       schedule iapp_wr_en_n CF iapp_wr_data;
+       schedule osdr_cke CF iapp_wr_en_n;
+       schedule osdr_cs_n CF iapp_wr_en_n;
+       schedule osdr_ras_n CF iapp_wr_en_n;
+       schedule osdr_cas_n CF iapp_wr_en_n;
+       schedule osdr_we_n CF iapp_wr_en_n;
+       schedule osdr_dqm CF iapp_wr_en_n;
+       schedule osdr_ba CF iapp_wr_en_n;
+       schedule osdr_addr CF iapp_wr_en_n;
+       schedule osdr_init_done CF iapp_wr_en_n;
+       schedule oapp_req_ack CF iapp_wr_en_n;
+       schedule oapp_wr_next_req CF iapp_wr_en_n;
+       schedule oapp_rd_valid CF iapp_wr_en_n;
+       schedule oapp_last_rd CF iapp_wr_en_n;
+       schedule oapp_last_wr CF iapp_wr_en_n;
+       schedule oapp_rd_data CF iapp_wr_en_n;
+    schedule osdr_dout CF iapp_wr_en_n;
+    schedule osdr_den_n CF iapp_wr_en_n;
+
+    schedule iapp_wr_data C iapp_wr_data;
+       schedule osdr_cke CF iapp_wr_data;
+       schedule osdr_cs_n CF iapp_wr_data;
+       schedule osdr_ras_n CF iapp_wr_data;
+       schedule osdr_cas_n CF iapp_wr_data;
+       schedule osdr_we_n CF iapp_wr_data;
+       schedule osdr_dqm CF iapp_wr_data;
+       schedule osdr_ba CF iapp_wr_data;
+       schedule osdr_addr CF iapp_wr_data;
+       schedule osdr_init_done CF iapp_wr_data;
+       schedule oapp_req_ack CF iapp_wr_data;
+       schedule oapp_wr_next_req CF iapp_wr_data;
+       schedule oapp_rd_valid CF iapp_wr_data;
+       schedule oapp_last_rd CF iapp_wr_data;
+       schedule oapp_last_wr CF iapp_wr_data;
+       schedule oapp_rd_data CF iapp_wr_data;
+    schedule osdr_dout CF iapp_wr_data;
+    schedule osdr_den_n CF iapp_wr_data;
+
+       schedule osdr_cke CF osdr_cke;
+       schedule osdr_cke CF osdr_cs_n;
+       schedule osdr_cke CF osdr_ras_n;
+       schedule osdr_cke CF osdr_cas_n;
+       schedule osdr_cke CF osdr_we_n;
+       schedule osdr_cke CF osdr_dqm;
+       schedule osdr_cke CF osdr_ba;
+       schedule osdr_cke CF osdr_addr;
+       schedule osdr_cke CF osdr_init_done;
+       schedule osdr_cke CF oapp_req_ack;
+       schedule osdr_cke CF oapp_wr_next_req;
+       schedule osdr_cke CF oapp_rd_valid;
+       schedule osdr_cke CF oapp_last_rd;
+       schedule osdr_cke CF oapp_last_wr;
+       schedule osdr_cke CF oapp_rd_data;
+       schedule osdr_cs_n CF osdr_cs_n;
+       schedule osdr_cs_n CF osdr_ras_n;
+       schedule osdr_cs_n CF osdr_cas_n;
+       schedule osdr_cs_n CF osdr_we_n;
+       schedule osdr_cs_n CF osdr_dqm;
+       schedule osdr_cs_n CF osdr_ba;
+       schedule osdr_cs_n CF osdr_addr;
+       schedule osdr_cs_n CF osdr_init_done;
+       schedule osdr_cs_n CF oapp_req_ack;
+       schedule osdr_cs_n CF oapp_wr_next_req;
+       schedule osdr_cs_n CF oapp_rd_valid;
+       schedule osdr_cs_n CF oapp_last_rd;
+       schedule osdr_cs_n CF oapp_last_wr;
+       schedule osdr_cs_n CF oapp_rd_data;
+       schedule osdr_ras_n CF osdr_ras_n;
+       schedule osdr_ras_n CF osdr_cas_n;
+       schedule osdr_ras_n CF osdr_we_n;
+       schedule osdr_ras_n CF osdr_dqm;
+       schedule osdr_ras_n CF osdr_ba;
+       schedule osdr_ras_n CF osdr_addr;
+       schedule osdr_ras_n CF osdr_init_done;
+       schedule osdr_ras_n CF oapp_req_ack;
+       schedule osdr_ras_n CF oapp_wr_next_req;
+       schedule osdr_ras_n CF oapp_rd_valid;
+       schedule osdr_ras_n CF oapp_last_rd;
+       schedule osdr_ras_n CF oapp_last_wr;
+       schedule osdr_ras_n CF oapp_rd_data;
+       schedule osdr_cas_n CF osdr_cas_n;
+       schedule osdr_cas_n CF osdr_we_n;
+       schedule osdr_cas_n CF osdr_dqm;
+       schedule osdr_cas_n CF osdr_ba;
+       schedule osdr_cas_n CF osdr_addr;
+       schedule osdr_cas_n CF osdr_init_done;
+       schedule osdr_cas_n CF oapp_req_ack;
+       schedule osdr_cas_n CF oapp_wr_next_req;
+       schedule osdr_cas_n CF oapp_rd_valid;
+       schedule osdr_cas_n CF oapp_last_rd;
+       schedule osdr_cas_n CF oapp_last_wr;
+       schedule osdr_cas_n CF oapp_rd_data;
+       schedule osdr_we_n CF osdr_we_n;
+       schedule osdr_we_n CF osdr_dqm;
+       schedule osdr_we_n CF osdr_ba;
+       schedule osdr_we_n CF osdr_addr;
+       schedule osdr_we_n CF osdr_init_done;
+       schedule osdr_we_n CF oapp_req_ack;
+       schedule osdr_we_n CF oapp_wr_next_req;
+       schedule osdr_we_n CF oapp_rd_valid;
+       schedule osdr_we_n CF oapp_last_rd;
+       schedule osdr_we_n CF oapp_last_wr;
+       schedule osdr_we_n CF oapp_rd_data;
+       schedule osdr_dqm CF osdr_dqm;
+       schedule osdr_dqm CF osdr_ba;
+       schedule osdr_dqm CF osdr_addr;
+       schedule osdr_dqm CF osdr_init_done;
+       schedule osdr_dqm CF oapp_req_ack;
+       schedule osdr_dqm CF oapp_wr_next_req;
+       schedule osdr_dqm CF oapp_rd_valid;
+       schedule osdr_dqm CF oapp_last_rd;
+       schedule osdr_dqm CF oapp_last_wr;
+       schedule osdr_dqm CF oapp_rd_data;
+       schedule osdr_ba CF osdr_ba;
+       schedule osdr_ba CF osdr_addr;
+       schedule osdr_ba CF osdr_init_done;
+       schedule osdr_ba CF oapp_req_ack;
+       schedule osdr_ba CF oapp_wr_next_req;
+       schedule osdr_ba CF oapp_rd_valid;
+       schedule osdr_ba CF oapp_last_rd;
+       schedule osdr_ba CF oapp_last_wr;
+       schedule osdr_ba CF oapp_rd_data;
+       schedule osdr_addr CF osdr_addr;
+       schedule osdr_addr CF osdr_init_done;
+       schedule osdr_addr CF oapp_req_ack;
+       schedule osdr_addr CF oapp_wr_next_req;
+       schedule osdr_addr CF oapp_rd_valid;
+       schedule osdr_addr CF oapp_last_rd;
+       schedule osdr_addr CF oapp_last_wr;
+       schedule osdr_addr CF oapp_rd_data;
+       schedule osdr_init_done CF osdr_init_done;
+       schedule osdr_init_done CF oapp_req_ack;
+       schedule osdr_init_done CF oapp_wr_next_req;
+       schedule osdr_init_done CF oapp_rd_valid;
+       schedule osdr_init_done CF oapp_last_rd;
+       schedule osdr_init_done CF oapp_last_wr;
+       schedule osdr_init_done CF oapp_rd_data;
+       schedule oapp_req_ack CF oapp_req_ack;
+       schedule oapp_req_ack CF oapp_wr_next_req;
+       schedule oapp_req_ack CF oapp_rd_valid;
+       schedule oapp_req_ack CF oapp_last_rd;
+       schedule oapp_req_ack CF oapp_last_wr;
+       schedule oapp_req_ack CF oapp_rd_data;
+       schedule oapp_wr_next_req CF oapp_wr_next_req;
+       schedule oapp_wr_next_req CF oapp_rd_valid;
+       schedule oapp_wr_next_req CF oapp_last_rd;
+       schedule oapp_wr_next_req CF oapp_last_wr;
+       schedule oapp_wr_next_req CF oapp_rd_data;
+       schedule oapp_rd_valid CF oapp_rd_valid;
+       schedule oapp_rd_valid CF oapp_last_rd;
+       schedule oapp_rd_valid CF oapp_last_wr;
+       schedule oapp_rd_valid CF oapp_rd_data;
+       schedule oapp_last_rd CF oapp_last_rd;
+       schedule oapp_last_rd CF oapp_last_wr;
+       schedule oapp_last_rd CF oapp_rd_data;
+       schedule oapp_last_wr CF oapp_last_wr;
+       schedule oapp_last_wr CF oapp_rd_data;
+       schedule oapp_rd_data CF oapp_rd_data;
+endmodule
+
diff --git a/src/peripherals/sdram/controller/parallel_prog_delay_cell.v b/src/peripherals/sdram/controller/parallel_prog_delay_cell.v
new file mode 100755 (executable)
index 0000000..068b66b
--- /dev/null
@@ -0,0 +1,42 @@
+
+module parallel_prog_delay_cell ( in_clk, delay_config_reg, delayed_clk);
+    input in_clk;
+    input [3:0] delay_config_reg;
+    output delayed_clk;
+
+    wire [7:0] wr_temp_delayed_clk;
+       wire xor_outp_clk;
+
+       xor(xor_outp_clk, delay_config_reg[3], in_clk);
+
+       assign wr_temp_delayed_clk[0]= xor_outp_clk;
+       delay_chain#(3) chain1 (.out(wr_temp_delayed_clk[1]),.in(xor_outp_clk));
+       delay_chain#(6) chain2 (.out(wr_temp_delayed_clk[2]),.in(xor_outp_clk));
+       delay_chain#(12) chain3 (.out(wr_temp_delayed_clk[3]),.in(xor_outp_clk));
+       delay_chain#(18) chain4 (.out(wr_temp_delayed_clk[4]),.in(xor_outp_clk));
+       delay_chain#(26) chain5 (.out(wr_temp_delayed_clk[5]),.in(xor_outp_clk));
+       delay_chain#(38) chain6 (.out(wr_temp_delayed_clk[6]),.in(xor_outp_clk));
+       delay_chain#(50) chain7 (.out(wr_temp_delayed_clk[7]),.in(xor_outp_clk));
+
+       assign delayed_clk= wr_temp_delayed_clk[delay_config_reg[2:0]];
+
+endmodule
+
+module delay_chain (in, out);
+       parameter Depth=0;
+       input in;
+       output out;
+       wire [Depth-1:0] wr_inter;
+
+       buf(wr_inter[0],in); // replace this with the buffer from the ASIC library
+       genvar i;
+       generate 
+               for(i=1; i<= Depth-1; i=i+1)
+               begin: gen_delay_buffer_chains
+                       buf(wr_inter[i],wr_inter[i-1]); // replace this with the buffer form the ASIC library.
+               end
+       endgenerate
+
+       assign out= wr_inter[Depth-1];
+endmodule
+
diff --git a/src/peripherals/sdram/controller/sdrc_bank_ctl.v b/src/peripherals/sdram/controller/sdrc_bank_ctl.v
new file mode 100755 (executable)
index 0000000..96fe94b
--- /dev/null
@@ -0,0 +1,602 @@
+/*********************************************************************
+                                                              
+  SDRAM Controller Bank Controller
+                                                              
+  This file is part of the sdram controller project           
+  http://www.opencores.org/cores/sdr_ctrl/                    
+                                                              
+  Description: 
+    This module takes requests from sdrc_req_gen, checks for page hit/miss and
+    issues precharge/activate commands and then passes the request to sdrc_xfr_ctl. 
+                                                              
+  To Do:                                                      
+    nothing                                                   
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesha@opencores.org                 
+  Version  :  1.0  - 8th Jan 2012
+                                                              
+
+                                                             
+ Copyright (C) 2000 Authors and OPENCORES.ORG                
+                                                             
+ This source file may be used and distributed without         
+ restriction provided that this copyright statement is not    
+ removed from the file and that any derivative work contains  
+ the original copyright notice and the associated disclaimer. 
+                                                              
+ This source file is free software; you can redistribute it   
+ and/or modify it under the terms of the GNU Lesser General   
+ Public License as published by the Free Software Foundation; 
+ either version 2.1 of the License, or (at your option) any   
+later version.                                               
+                                                              
+ This source is distributed in the hope that it will be       
+ useful, but WITHOUT ANY WARRANTY; without even the implied   
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+ PURPOSE.  See the GNU Lesser General Public License for more 
+ details.                                                     
+                                                              
+ You should have received a copy of the GNU Lesser General    
+ Public License along with this source; if not, download it   
+ from http://www.opencores.org/lgpl.shtml                     
+                                                              
+*******************************************************************/
+
+
+
+
+module sdrc_bank_ctl (clk,
+                    reset_n,
+                    a2b_req_depth,  // Number of requests we can buffer
+
+                    /* Req from req_gen */
+                    r2b_req,      // request
+                    r2b_req_id,   // ID
+                    r2b_start,    // First chunk of burst
+                    r2b_last,     // Last chunk of burst
+                    r2b_wrap,
+                    r2b_ba,       // bank address
+                    r2b_raddr,    // row address
+                    r2b_caddr,    // col address
+                    r2b_len,      // length
+                    r2b_write,    // write request
+                    b2r_arb_ok,   // OK to arbitrate for next xfr
+                    b2r_ack,
+
+                    /* Transfer request to xfr_ctl */
+                    b2x_idle,     // All banks are idle
+                    b2x_req,      // Request to xfr_ctl
+                    b2x_start,    // first chunk of transfer
+                    b2x_last,     // last chunk of transfer
+                    b2x_wrap,
+                    b2x_id,       // Transfer ID
+                    b2x_ba,       // bank address
+                    b2x_addr,     // row/col address
+                    b2x_len,      // transfer length
+                    b2x_cmd,      // transfer command
+                    x2b_ack,      // command accepted
+                    
+                    /* Status to/from xfr_ctl */
+                    b2x_tras_ok,  // TRAS OK for all banks
+                    x2b_refresh,  // We did a refresh
+                    x2b_pre_ok,   // OK to do a precharge (per bank)
+                    x2b_act_ok,   // OK to do an activate
+                    x2b_rdok,     // OK to do a read
+                    x2b_wrok,     // OK to do a write
+
+                    /* xfr msb address */
+                    xfr_bank_sel,
+                     sdr_req_norm_dma_last,
+
+                    /* SDRAM Timing */
+                    tras_delay,   // Active to precharge delay
+                    trp_delay,    // Precharge to active delay
+                    trcd_delay);  // Active to R/W delay
+
+`define SDR_REQ_ID_W       4
+
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W   3
+
+// B2X Command
+
+`define OP_PRE           2'b00
+`define OP_ACT           2'b01
+`define OP_RD            2'b10
+`define OP_WR            2'b11
+
+// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
+
+`define SDR_DESEL        4'b1111
+`define SDR_NOOP         4'b0111
+`define SDR_ACTIVATE     4'b0011
+`define SDR_READ         4'b0101
+`define SDR_WRITE        4'b0100
+`define SDR_BT           4'b0110
+`define SDR_PRECHARGE    4'b0010
+`define SDR_REFRESH      4'b0001
+`define SDR_MODE         4'b0000
+
+`define  ASIC            1'b1
+`define  FPGA            1'b0
+`define  TARGET_DESIGN   `ASIC
+// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
+`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
+
+   
+parameter  SDR_DW   = 64;  // SDR Data Width 
+parameter  SDR_BW   = 8;   // SDR Byte Width
+   input                        clk, reset_n;
+
+   input [1:0]                         a2b_req_depth;
+   
+   /* Req from bank_ctl */
+   input                       r2b_req, r2b_start, r2b_last,
+                               r2b_write, r2b_wrap;
+   input [`SDR_REQ_ID_W-1:0]   r2b_req_id;
+   input [1:0]                         r2b_ba;
+   input [12:0]                r2b_raddr;
+   input [12:0]                r2b_caddr;
+   input [`REQ_BW-1:0]                 r2b_len;
+   output                      b2r_arb_ok, b2r_ack;
+   input                        sdr_req_norm_dma_last;
+
+   /* Req to xfr_ctl */
+   output                      b2x_idle, b2x_req, b2x_start, b2x_last,
+                               b2x_tras_ok, b2x_wrap;
+   output [`SDR_REQ_ID_W-1:0]  b2x_id;
+   output [1:0]                b2x_ba;
+   output [12:0]               b2x_addr;
+   output [`REQ_BW-1:0]        b2x_len;
+   output [1:0]                b2x_cmd;
+   input                       x2b_ack;
+
+   /* Status from xfr_ctl */
+   input [3:0]                         x2b_pre_ok;
+   input                       x2b_refresh, x2b_act_ok, x2b_rdok,
+                               x2b_wrok;
+   
+   input [3:0]                         tras_delay, trp_delay, trcd_delay;
+
+   input [1:0] xfr_bank_sel;
+
+   /****************************************************************************/
+   // Internal Nets
+
+   wire [3:0]                  r2i_req, i2r_ack, i2x_req, 
+                               i2x_start, i2x_last, i2x_wrap, tras_ok;
+   wire [12:0]                         i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
+   wire [`REQ_BW-1:0]  i2x_len0, i2x_len1, i2x_len2, i2x_len3;
+   wire [1:0]                  i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
+   wire [`SDR_REQ_ID_W-1:0]    i2x_id0, i2x_id1, i2x_id2, i2x_id3;
+
+   reg                                 b2x_req;
+   wire                        b2x_idle, b2x_start, b2x_last, b2x_wrap;
+   wire [`SDR_REQ_ID_W-1:0]    b2x_id;
+   wire [12:0]                         b2x_addr;
+   wire [`REQ_BW-1:0]  b2x_len;
+   wire [1:0]                  b2x_cmd;
+   wire [3:0]                  x2i_ack;
+   reg [1:0]                   b2x_ba;
+   
+   reg [`SDR_REQ_ID_W-1:0]     curr_id;
+
+   wire [1:0]                  xfr_ba;
+   wire                        xfr_ba_last;
+   wire [3:0]                  xfr_ok;
+
+   // This 8 bit register stores the bank addresses for upto 4 requests.
+   reg [7:0]                   rank_ba;
+   reg [3:0]                   rank_ba_last;
+   // This 3 bit counter counts the number of requests we have
+   // buffered so far, legal values are 0, 1, 2, 3, or 4.
+   reg [2:0]                   rank_cnt;
+   wire [3:0]                  rank_req, rank_wr_sel;
+   wire                        rank_fifo_wr, rank_fifo_rd;
+   wire                        rank_fifo_full, rank_fifo_mt;
+   
+   wire [12:0] bank0_row, bank1_row, bank2_row, bank3_row;
+
+   assign  b2x_tras_ok        = &tras_ok;
+
+
+   // Distribute the request from req_gen
+
+   assign r2i_req[0] = (r2b_ba == 2'b00) ? r2b_req & ~rank_fifo_full : 1'b0;
+   assign r2i_req[1] = (r2b_ba == 2'b01) ? r2b_req & ~rank_fifo_full : 1'b0;
+   assign r2i_req[2] = (r2b_ba == 2'b10) ? r2b_req & ~rank_fifo_full : 1'b0;
+   assign r2i_req[3] = (r2b_ba == 2'b11) ? r2b_req & ~rank_fifo_full : 1'b0;
+
+   /******************
+   Modified the Better FPGA Timing Purpose
+   assign b2r_ack = (r2b_ba == 2'b00) ? i2r_ack[0] :
+                   (r2b_ba == 2'b01) ? i2r_ack[1] :
+                   (r2b_ba == 2'b10) ? i2r_ack[2] :
+                   (r2b_ba == 2'b11) ? i2r_ack[3] : 1'b0;
+   ********************/
+   // Assumption: Only one Ack Will be asserted at a time.
+   assign b2r_ack  =|i2r_ack; 
+
+   assign b2r_arb_ok = ~rank_fifo_full;
+   
+   // Put the requests from the 4 bank_fsms into a 4 deep shift
+   // register file. The earliest request is prioritized over the
+   // later requests. Also the number of requests we are allowed to
+   // buffer is limited by a 2 bit external input
+   
+   // Mux the req/cmd to xfr_ctl. Allow RD/WR commands from the request in
+   // rank0, allow only PR/ACT commands from the requests in other ranks
+   // If the rank_fifo is empty, send the request from the bank addressed by
+   // r2b_ba 
+
+   // In FPGA Mode, to improve the timing, also send the rank_ba
+   assign xfr_ba = (`TARGET_DESIGN == `FPGA) ? rank_ba[1:0]:
+                  ((rank_fifo_mt) ? r2b_ba : rank_ba[1:0]);
+   assign xfr_ba_last = (`TARGET_DESIGN == `FPGA) ? rank_ba_last[0]:
+                       ((rank_fifo_mt) ? sdr_req_norm_dma_last : rank_ba_last[0]);
+   
+   assign rank_req[0] = i2x_req[xfr_ba];     // each rank generates requests
+                       
+   assign rank_req[1] = (rank_cnt < 3'h2) ? 1'b0 :
+                       (rank_ba[3:2] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
+                       (rank_ba[3:2] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
+                       (rank_ba[3:2] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] : 
+                       i2x_req[3] & ~i2x_cmd3[1];
+                       
+   assign rank_req[2] = (rank_cnt < 3'h3) ? 1'b0 :
+                       (rank_ba[5:4] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
+                       (rank_ba[5:4] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
+                       (rank_ba[5:4] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] : 
+                       i2x_req[3] & ~i2x_cmd3[1];
+                       
+   assign rank_req[3] = (rank_cnt < 3'h4) ? 1'b0 :
+                       (rank_ba[7:6] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] :
+                       (rank_ba[7:6] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] :
+                       (rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] : 
+                       i2x_req[3] & ~i2x_cmd3[1];
+                       
+   always @ (*) begin
+      b2x_req = 1'b0;
+      b2x_ba =   xfr_ba;
+
+      if(`TARGET_DESIGN == `ASIC) begin // Support Multiple Rank request only on ASIC
+         if (rank_req[0]) begin 
+           b2x_req = 1'b1;
+           b2x_ba = xfr_ba;
+         end // if (rank_req[0])
+        else if (rank_req[1]) begin 
+          b2x_req = 1'b1;
+          b2x_ba = rank_ba[3:2];
+        end // if (rank_req[1])
+        else if (rank_req[2]) begin 
+         b2x_req = 1'b1;
+         b2x_ba = rank_ba[5:4];
+        end // if (rank_req[2])
+        else if (rank_req[3]) begin 
+         b2x_req = 1'b1;
+         b2x_ba = rank_ba[7:6];
+        end // if (rank_req[3])
+      end else begin // If FPGA
+         if (rank_req[0]) begin 
+           b2x_req = 1'b1;
+        end
+      end
+  end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
+
+   assign b2x_idle = rank_fifo_mt;
+   assign b2x_start = i2x_start[b2x_ba];
+   assign b2x_last = i2x_last[b2x_ba];
+   assign b2x_wrap = i2x_wrap[b2x_ba];
+
+   assign b2x_addr = (b2x_ba == 2'b11) ? i2x_addr3 :
+                    (b2x_ba == 2'b10) ? i2x_addr2 :
+                    (b2x_ba == 2'b01) ? i2x_addr1 : i2x_addr0;
+   
+   assign b2x_len = (b2x_ba == 2'b11) ? i2x_len3 :
+                   (b2x_ba == 2'b10) ? i2x_len2 :
+                   (b2x_ba == 2'b01) ? i2x_len1 : i2x_len0;
+   
+   assign b2x_cmd = (b2x_ba == 2'b11) ? i2x_cmd3 :
+                   (b2x_ba == 2'b10) ? i2x_cmd2 :
+                   (b2x_ba == 2'b01) ? i2x_cmd1 : i2x_cmd0;
+   
+   assign b2x_id = (b2x_ba == 2'b11) ? i2x_id3 :
+                  (b2x_ba == 2'b10) ? i2x_id2 :
+                  (b2x_ba == 2'b01) ? i2x_id1 : i2x_id0;
+   
+   assign x2i_ack[0] = (b2x_ba == 2'b00) ? x2b_ack : 1'b0;
+   assign x2i_ack[1] = (b2x_ba == 2'b01) ? x2b_ack : 1'b0;
+   assign x2i_ack[2] = (b2x_ba == 2'b10) ? x2b_ack : 1'b0;
+   assign x2i_ack[3] = (b2x_ba == 2'b11) ? x2b_ack : 1'b0;
+
+   // Rank Fifo
+   // On a write write to selected rank and increment rank_cnt
+   // On a read shift rank_ba right 2 bits and decrement rank_cnt
+
+   assign rank_fifo_wr = b2r_ack;
+
+   assign rank_fifo_rd = b2x_req & b2x_cmd[1] & x2b_ack;
+   
+   assign rank_wr_sel[0] = (rank_cnt == 3'h0) ? rank_fifo_wr : 
+                          (rank_cnt == 3'h1) ? rank_fifo_wr & rank_fifo_rd : 
+                          1'b0;
+
+   assign rank_wr_sel[1] = (rank_cnt == 3'h1) ? rank_fifo_wr & ~rank_fifo_rd :
+                          (rank_cnt == 3'h2) ? rank_fifo_wr & rank_fifo_rd :
+                          1'b0; 
+
+   assign rank_wr_sel[2] = (rank_cnt == 3'h2) ? rank_fifo_wr & ~rank_fifo_rd :
+                          (rank_cnt == 3'h3) ? rank_fifo_wr & rank_fifo_rd :
+                          1'b0; 
+
+   assign rank_wr_sel[3] = (rank_cnt == 3'h3) ? rank_fifo_wr & ~rank_fifo_rd :
+                          (rank_cnt == 3'h4) ? rank_fifo_wr & rank_fifo_rd :
+                          1'b0; 
+
+   assign rank_fifo_mt = (rank_cnt == 3'b0) ? 1'b1 : 1'b0;
+
+   assign rank_fifo_full = (rank_cnt[2]) ? 1'b1 : 
+                          (rank_cnt[1:0] == a2b_req_depth) ? 1'b1 : 1'b0; 
+
+   // FIFO Check
+
+   // synopsys translate_off
+
+   always @ (posedge clk) begin
+
+      if (~rank_fifo_wr & rank_fifo_rd && rank_cnt == 3'h0) begin
+        $display ("%t: %m: ERROR!!! Read from empty Fifo", $time);
+        $stop;
+      end // if (rank_fifo_rd && rank_cnt == 3'h0)
+
+      if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4) begin
+        $display ("%t: %m: ERROR!!! Write to full Fifo", $time);
+        $stop;
+      end // if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4)
+      
+   end // always @ (posedge clk)
+   
+   // synopsys translate_on
+      
+   always @ (posedge clk)
+      if (~reset_n) begin
+        rank_cnt <= 3'b0;
+        rank_ba <= 8'b0;
+        rank_ba_last <= 4'b0;
+
+      end // if (~reset_n)
+      else begin
+
+        rank_cnt <= (rank_fifo_wr & ~rank_fifo_rd) ? rank_cnt + 3'b1 :
+                    (~rank_fifo_wr & rank_fifo_rd) ? rank_cnt - 3'b1 :
+                    rank_cnt;
+
+        rank_ba[1:0] <= (rank_wr_sel[0]) ? r2b_ba :
+                        (rank_fifo_rd) ? rank_ba[3:2] : rank_ba[1:0];
+        
+        rank_ba[3:2] <= (rank_wr_sel[1]) ? r2b_ba :
+                        (rank_fifo_rd) ? rank_ba[5:4] : rank_ba[3:2];
+        
+        rank_ba[5:4] <= (rank_wr_sel[2]) ? r2b_ba :
+                        (rank_fifo_rd) ? rank_ba[7:6] : rank_ba[5:4];
+        
+        rank_ba[7:6] <= (rank_wr_sel[3]) ? r2b_ba :
+                        (rank_fifo_rd) ? 2'b00 : rank_ba[7:6];
+
+        if(`TARGET_DESIGN == `ASIC) begin // This Logic is implemented for ASIC Only
+           // Note: Currenly top-level does not generate the
+           // sdr_req_norm_dma_last signal and can be tied zero at top-level
+            rank_ba_last[0] <= (rank_wr_sel[0]) ? sdr_req_norm_dma_last :
+                            (rank_fifo_rd) ?  rank_ba_last[1] : rank_ba_last[0];
+
+            rank_ba_last[1] <= (rank_wr_sel[1]) ? sdr_req_norm_dma_last :
+                               (rank_fifo_rd) ?  rank_ba_last[2] : rank_ba_last[1];
+
+            rank_ba_last[2] <= (rank_wr_sel[2]) ? sdr_req_norm_dma_last :
+                               (rank_fifo_rd) ?  rank_ba_last[3] : rank_ba_last[2];
+
+            rank_ba_last[3] <= (rank_wr_sel[3]) ? sdr_req_norm_dma_last :
+                               (rank_fifo_rd) ?  1'b0 : rank_ba_last[3];
+         end
+
+      end // else: !if(~reset_n)
+   
+   assign xfr_ok[0] = (xfr_ba == 2'b00) ? 1'b1 : 1'b0;
+   assign xfr_ok[1] = (xfr_ba == 2'b01) ? 1'b1 : 1'b0;
+   assign xfr_ok[2] = (xfr_ba == 2'b10) ? 1'b1 : 1'b0;
+   assign xfr_ok[3] = (xfr_ba == 2'b11) ? 1'b1 : 1'b0;
+   
+   /****************************************************************************/
+   // Instantiate Bank Ctl FSM 0
+
+   sdrc_bank_fsm bank0_fsm (.clk (clk),
+                          .reset_n (reset_n),
+
+                          /* Req from req_gen */
+                          .r2b_req (r2i_req[0]),
+                          .r2b_req_id (r2b_req_id),
+                          .r2b_start (r2b_start),
+                          .r2b_last (r2b_last),
+                          .r2b_wrap (r2b_wrap),
+                          .r2b_raddr (r2b_raddr),
+                          .r2b_caddr (r2b_caddr),
+                          .r2b_len (r2b_len),
+                          .r2b_write (r2b_write),
+                          .b2r_ack (i2r_ack[0]),
+                           .sdr_dma_last(rank_ba_last[0]),
+
+                          /* Transfer request to xfr_ctl */
+                          .b2x_req (i2x_req[0]),
+                          .b2x_start (i2x_start[0]),
+                          .b2x_last (i2x_last[0]),
+                          .b2x_wrap (i2x_wrap[0]),
+                          .b2x_id (i2x_id0),
+                          .b2x_addr (i2x_addr0),
+                          .b2x_len (i2x_len0),
+                          .b2x_cmd (i2x_cmd0),
+                          .x2b_ack (x2i_ack[0]),
+                    
+                          /* Status to/from xfr_ctl */
+                          .tras_ok (tras_ok[0]),
+                          .xfr_ok (xfr_ok[0]),
+                          .x2b_refresh (x2b_refresh),
+                          .x2b_pre_ok (x2b_pre_ok[0]),
+                          .x2b_act_ok (x2b_act_ok),
+                          .x2b_rdok (x2b_rdok),
+                          .x2b_wrok (x2b_wrok),
+
+                          .bank_row(bank0_row),
+
+                          /* SDRAM Timing */
+                          .tras_delay (tras_delay),
+                          .trp_delay (trp_delay),
+                          .trcd_delay (trcd_delay));
+   
+   /****************************************************************************/
+   // Instantiate Bank Ctl FSM 1
+
+   sdrc_bank_fsm bank1_fsm (.clk (clk),
+                          .reset_n (reset_n),
+
+                          /* Req from req_gen */
+                          .r2b_req (r2i_req[1]),
+                          .r2b_req_id (r2b_req_id),
+                          .r2b_start (r2b_start),
+                          .r2b_last (r2b_last),
+                          .r2b_wrap (r2b_wrap),
+                          .r2b_raddr (r2b_raddr),
+                          .r2b_caddr (r2b_caddr),
+                          .r2b_len (r2b_len),
+                          .r2b_write (r2b_write),
+                          .b2r_ack (i2r_ack[1]),
+                           .sdr_dma_last(rank_ba_last[1]),
+
+                          /* Transfer request to xfr_ctl */
+                          .b2x_req (i2x_req[1]),
+                          .b2x_start (i2x_start[1]),
+                          .b2x_last (i2x_last[1]),
+                          .b2x_wrap (i2x_wrap[1]),
+                          .b2x_id (i2x_id1),
+                          .b2x_addr (i2x_addr1),
+                          .b2x_len (i2x_len1),
+                          .b2x_cmd (i2x_cmd1),
+                          .x2b_ack (x2i_ack[1]),
+                    
+                          /* Status to/from xfr_ctl */
+                          .tras_ok (tras_ok[1]),           
+                          .xfr_ok (xfr_ok[1]),
+                          .x2b_refresh (x2b_refresh),
+                          .x2b_pre_ok (x2b_pre_ok[1]),
+                          .x2b_act_ok (x2b_act_ok),
+                          .x2b_rdok (x2b_rdok),
+                          .x2b_wrok (x2b_wrok),
+
+                          .bank_row(bank1_row),
+
+                          /* SDRAM Timing */
+                          .tras_delay (tras_delay),
+                          .trp_delay (trp_delay),
+                          .trcd_delay (trcd_delay));
+   
+   /****************************************************************************/
+   // Instantiate Bank Ctl FSM 2
+
+   sdrc_bank_fsm bank2_fsm (.clk (clk),
+                          .reset_n (reset_n),
+
+                          /* Req from req_gen */
+                          .r2b_req (r2i_req[2]),
+                          .r2b_req_id (r2b_req_id),
+                          .r2b_start (r2b_start),
+                          .r2b_last (r2b_last),
+                          .r2b_wrap (r2b_wrap),
+                          .r2b_raddr (r2b_raddr),
+                          .r2b_caddr (r2b_caddr),
+                          .r2b_len (r2b_len),
+                          .r2b_write (r2b_write),
+                          .b2r_ack (i2r_ack[2]),
+                           .sdr_dma_last(rank_ba_last[2]),
+
+                          /* Transfer request to xfr_ctl */
+                          .b2x_req (i2x_req[2]),
+                          .b2x_start (i2x_start[2]),
+                          .b2x_last (i2x_last[2]),
+                          .b2x_wrap (i2x_wrap[2]),
+                          .b2x_id (i2x_id2),
+                          .b2x_addr (i2x_addr2),
+                          .b2x_len (i2x_len2),
+                          .b2x_cmd (i2x_cmd2),
+                          .x2b_ack (x2i_ack[2]),
+                    
+                          /* Status to/from xfr_ctl */
+                          .tras_ok (tras_ok[2]),           
+                          .xfr_ok (xfr_ok[2]),
+                          .x2b_refresh (x2b_refresh),
+                          .x2b_pre_ok (x2b_pre_ok[2]),
+                          .x2b_act_ok (x2b_act_ok),
+                          .x2b_rdok (x2b_rdok),
+                          .x2b_wrok (x2b_wrok),
+
+                          .bank_row(bank2_row),
+
+                          /* SDRAM Timing */
+                          .tras_delay (tras_delay),
+                          .trp_delay (trp_delay),
+                          .trcd_delay (trcd_delay));
+   
+   /****************************************************************************/
+   // Instantiate Bank Ctl FSM 3
+
+   sdrc_bank_fsm bank3_fsm (.clk (clk),
+                          .reset_n (reset_n),
+
+                          /* Req from req_gen */
+                          .r2b_req (r2i_req[3]),
+                          .r2b_req_id (r2b_req_id),
+                          .r2b_start (r2b_start),
+                          .r2b_last (r2b_last),
+                          .r2b_wrap (r2b_wrap),
+                          .r2b_raddr (r2b_raddr),
+                          .r2b_caddr (r2b_caddr),
+                          .r2b_len (r2b_len),
+                          .r2b_write (r2b_write),
+                          .b2r_ack (i2r_ack[3]),
+                           .sdr_dma_last(rank_ba_last[3]),
+
+                          /* Transfer request to xfr_ctl */
+                          .b2x_req (i2x_req[3]),
+                          .b2x_start (i2x_start[3]),
+                          .b2x_last (i2x_last[3]),
+                          .b2x_wrap (i2x_wrap[3]),
+                          .b2x_id (i2x_id3),
+                          .b2x_addr (i2x_addr3),
+                          .b2x_len (i2x_len3),
+                          .b2x_cmd (i2x_cmd3),
+                          .x2b_ack (x2i_ack[3]),
+                    
+                          /* Status to/from xfr_ctl */
+                          .tras_ok (tras_ok[3]),           
+                          .xfr_ok (xfr_ok[3]),
+                          .x2b_refresh (x2b_refresh),
+                          .x2b_pre_ok (x2b_pre_ok[3]),
+                          .x2b_act_ok (x2b_act_ok),
+                          .x2b_rdok (x2b_rdok),
+                          .x2b_wrok (x2b_wrok),
+
+                          .bank_row(bank3_row),
+
+                          /* SDRAM Timing */
+                          .tras_delay (tras_delay),
+                          .trp_delay (trp_delay),
+                          .trcd_delay (trcd_delay));
+   
+
+/* address for current xfr, debug only */
+wire [12:0] cur_row = (xfr_bank_sel==3) ? bank3_row:
+                       (xfr_bank_sel==2) ? bank2_row: 
+                       (xfr_bank_sel==1) ? bank1_row: bank0_row; 
+
+
+endmodule // sdr_bank_ctl
diff --git a/src/peripherals/sdram/controller/sdrc_bank_fsm.v b/src/peripherals/sdram/controller/sdrc_bank_fsm.v
new file mode 100755 (executable)
index 0000000..7ac177d
--- /dev/null
@@ -0,0 +1,401 @@
+/*********************************************************************
+                                                              
+  SDRAM Controller Bank Controller
+                                                              
+  This file is part of the sdram controller project           
+  http://www.opencores.org/cores/sdr_ctrl/                    
+                                                              
+  Description: 
+    This module takes requests from sdrc_req_gen, checks for page hit/miss and
+    issues precharge/activate commands and then passes the request to sdrc_xfr_ctl. 
+                                                              
+  To Do:                                                      
+    nothing                                                   
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesha@opencores.org                 
+  Version  :  1.0  - 8th Jan 2012
+                                                              
+
+                                                             
+ Copyright (C) 2000 Authors and OPENCORES.ORG                
+                                                             
+ This source file may be used and distributed without         
+ restriction provided that this copyright statement is not    
+ removed from the file and that any derivative work contains  
+ the original copyright notice and the associated disclaimer. 
+                                                              
+ This source file is free software; you can redistribute it   
+ and/or modify it under the terms of the GNU Lesser General   
+ Public License as published by the Free Software Foundation; 
+ either version 2.1 of the License, or (at your option) any   
+later version.                                               
+                                                              
+ This source is distributed in the hope that it will be       
+ useful, but WITHOUT ANY WARRANTY; without even the implied   
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+ PURPOSE.  See the GNU Lesser General Public License for more 
+ details.                                                     
+                                                              
+ You should have received a copy of the GNU Lesser General    
+ Public License along with this source; if not, download it   
+ from http://www.opencores.org/lgpl.shtml                     
+                                                              
+*******************************************************************/
+
+
+//`include "sdrc_define.v"
+
+module sdrc_bank_fsm (clk,
+                    reset_n,
+
+                    /* Req from req_gen */
+                    r2b_req,      // request
+                    r2b_req_id,   // ID
+                    r2b_start,    // First chunk of burst
+                    r2b_last,     // Last chunk of burst
+                    r2b_wrap,
+                    r2b_raddr,    // row address
+                    r2b_caddr,    // col address
+                    r2b_len,      // length
+                    r2b_write,    // write request
+                    b2r_ack,
+                     sdr_dma_last,
+
+                    /* Transfer request to xfr_ctl */
+                    b2x_req,      // Request to xfr_ctl
+                    b2x_start,    // first chunk of transfer
+                    b2x_last,     // last chunk of transfer
+                    b2x_wrap,
+                    b2x_id,       // Transfer ID
+                    b2x_addr,     // row/col address
+                    b2x_len,      // transfer length
+                    b2x_cmd,      // transfer command
+                    x2b_ack,      // command accepted
+                    
+                    /* Status to/from xfr_ctl */
+                    tras_ok,      // TRAS OK for this bank
+                    xfr_ok,
+                    x2b_refresh,  // We did a refresh
+                    x2b_pre_ok,   // OK to do a precharge (per bank)
+                    x2b_act_ok,   // OK to do an activate
+                    x2b_rdok,     // OK to do a read
+                    x2b_wrok,     // OK to do a write
+
+                    /* current xfr row address of the bank */
+                    bank_row,
+
+                    /* SDRAM Timing */
+                    tras_delay,   // Active to precharge delay
+                    trp_delay,    // Precharge to active delay
+                    trcd_delay);  // Active to R/W delay
+   
+
+`define SDR_REQ_ID_W       4
+
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W   3
+
+// B2X Command
+
+`define OP_PRE           2'b00
+`define OP_ACT           2'b01
+`define OP_RD            2'b10
+`define OP_WR            2'b11
+
+// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
+
+`define SDR_DESEL        4'b1111
+`define SDR_NOOP         4'b0111
+`define SDR_ACTIVATE     4'b0011
+`define SDR_READ         4'b0101
+`define SDR_WRITE        4'b0100
+`define SDR_BT           4'b0110
+`define SDR_PRECHARGE    4'b0010
+`define SDR_REFRESH      4'b0001
+`define SDR_MODE         4'b0000
+
+`define  ASIC            1'b1
+`define  FPGA            1'b0
+`define  TARGET_DESIGN   `ASIC
+// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
+`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
+
+parameter  SDR_DW   = 64;  // SDR Data Width 
+parameter  SDR_BW   = 8;   // SDR Byte Width
+
+   input                        clk, reset_n;
+
+   /* Req from bank_ctl */
+   input                       r2b_req, r2b_start, r2b_last,
+                               r2b_write, r2b_wrap;
+   input [`SDR_REQ_ID_W-1:0]   r2b_req_id;
+   input [12:0]                r2b_raddr;
+   input [12:0]                r2b_caddr;
+   input [`REQ_BW-1:0]         r2b_len;
+   output                      b2r_ack;
+   input                        sdr_dma_last;
+
+   /* Req to xfr_ctl */
+   output                      b2x_req, b2x_start, b2x_last,
+                               tras_ok, b2x_wrap;
+   output [`SDR_REQ_ID_W-1:0]  b2x_id;
+   output [12:0]               b2x_addr;
+   output [`REQ_BW-1:0]        b2x_len;
+   output [1:0]                b2x_cmd;
+   input                       x2b_ack;
+
+   /* Status from xfr_ctl */
+   input                       x2b_refresh, x2b_act_ok, x2b_rdok,
+                               x2b_wrok, x2b_pre_ok, xfr_ok;
+   
+   input [3:0]                         tras_delay, trp_delay, trcd_delay;
+
+   output [12:0]                       bank_row;
+
+   /****************************************************************************/
+   // Internal Nets
+
+   `define BANK_IDLE         3'b000
+   `define BANK_PRE          3'b001
+   `define BANK_ACT          3'b010
+   `define BANK_XFR          3'b011
+   `define BANK_DMA_LAST_PRE 3'b100
+
+   reg [2:0]                   bank_st, next_bank_st;
+   wire                        b2x_start, b2x_last;
+   reg                                 l_start, l_last;
+   reg                                 b2x_req, b2r_ack;
+   wire [`SDR_REQ_ID_W-1:0]    b2x_id;
+   reg [`SDR_REQ_ID_W-1:0]     l_id;
+   reg [12:0]                  b2x_addr;
+   reg [`REQ_BW-1:0]   l_len;
+   wire [`REQ_BW-1:0]  b2x_len;
+   reg [1:0]                   b2x_cmd_t;
+   reg                         bank_valid;
+   reg [12:0]                  bank_row;
+   reg [3:0]                   tras_cntr, timer0;
+   reg                                 l_wrap, l_write;
+   wire                        b2x_wrap;
+   reg [12:0]                  l_raddr;
+   reg [12:0]                  l_caddr;
+   reg                          l_sdr_dma_last;
+   reg                          bank_prech_page_closed;
+   
+   wire                        tras_ok_internal, tras_ok, activate_bank;
+   
+   wire                        page_hit, timer0_tc_t, ld_trp, ld_trcd;
+
+   /*** Timing Break Logic Added for FPGA - Start ****/
+   reg x2b_wrok_r, xfr_ok_r , x2b_rdok_r;
+   reg [1:0] b2x_cmd_r,timer0_tc_r,tras_ok_r,x2b_pre_ok_r,x2b_act_ok_r;
+   always @ (posedge clk)
+      if (~reset_n) begin
+        x2b_wrok_r <= 1'b0;
+        xfr_ok_r   <= 1'b0;
+        x2b_rdok_r <= 1'b0;
+        b2x_cmd_r  <= 2'b0;
+        timer0_tc_r  <= 1'b0;
+        tras_ok_r    <= 1'b0;
+        x2b_pre_ok_r <= 1'b0;
+        x2b_act_ok_r <= 1'b0;
+      end
+      else begin
+        x2b_wrok_r <= x2b_wrok;
+        xfr_ok_r   <= xfr_ok;
+        x2b_rdok_r <= x2b_rdok;
+        b2x_cmd_r  <= b2x_cmd_t;
+        timer0_tc_r <= (ld_trp | ld_trcd) ? 1'b0 : timer0_tc_t;
+        tras_ok_r   <= tras_ok_internal;
+        x2b_pre_ok_r  <= x2b_pre_ok;
+        x2b_act_ok_r  <= x2b_act_ok;
+      end
+
+ wire  x2b_wrok_t     = (`TARGET_DESIGN == `FPGA) ? x2b_wrok_r : x2b_wrok;
+ wire  xfr_ok_t       = (`TARGET_DESIGN == `FPGA) ? xfr_ok_r : xfr_ok;
+ wire  x2b_rdok_t     = (`TARGET_DESIGN == `FPGA) ? x2b_rdok_r : x2b_rdok;
+ wire [1:0] b2x_cmd   = (`TARGET_DESIGN == `FPGA) ? b2x_cmd_r : b2x_cmd_t;
+ wire  timer0_tc      = (`TARGET_DESIGN == `FPGA) ? timer0_tc_r : timer0_tc_t;
+ assign  tras_ok      = (`TARGET_DESIGN == `FPGA) ? tras_ok_r : tras_ok_internal;
+ wire  x2b_pre_ok_t   = (`TARGET_DESIGN == `FPGA) ? x2b_pre_ok_r : x2b_pre_ok;
+ wire  x2b_act_ok_t   = (`TARGET_DESIGN == `FPGA) ? x2b_act_ok_r : x2b_act_ok;
+
+   /*** Timing Break Logic Added for FPGA - End****/
+
+
+   always @ (posedge clk)
+      if (~reset_n) begin
+        bank_valid <= 1'b0;
+        tras_cntr <= 4'b0;
+        timer0 <= 4'b0;
+        bank_st <= `BANK_IDLE;
+      end // if (~reset_n)
+
+      else begin
+
+        bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 :  // force the bank status to be invalid
+                      (activate_bank) ? 1'b1 : bank_valid;
+
+        tras_cntr <= (activate_bank) ? tras_delay :
+                     (~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0;
+        
+        timer0 <= (ld_trp) ? trp_delay :
+                  (ld_trcd) ? trcd_delay :
+                  (timer0 != 'h0) ? timer0 - 4'b1 : timer0;
+        
+        bank_st <= next_bank_st;
+
+      end // else: !if(~reset_n)
+
+   always @ (posedge clk) begin 
+
+      bank_row <= (bank_st == `BANK_ACT) ? b2x_addr : bank_row;
+
+      if (~reset_n) begin
+        l_start <= 1'b0;
+        l_last <= 1'b0;
+        l_id <= 1'b0;
+        l_len <= 1'b0;
+        l_wrap <= 1'b0;
+        l_write <= 1'b0;
+        l_raddr <= 1'b0;
+        l_caddr <= 1'b0;
+         l_sdr_dma_last <= 1'b0;
+      end
+      else begin
+        if (b2r_ack) begin
+          l_start <= r2b_start;
+          l_last <= r2b_last;
+          l_id <= r2b_req_id;
+          l_len <= r2b_len;
+          l_wrap <= r2b_wrap;
+          l_write <= r2b_write;
+          l_raddr <= r2b_raddr;
+          l_caddr <= r2b_caddr;
+           l_sdr_dma_last <= sdr_dma_last;
+        end // if (b2r_ack)
+      end
+
+   end // always @ (posedge clk)
+   
+   assign tras_ok_internal = ~|tras_cntr;
+
+   assign activate_bank = (b2x_cmd == `OP_ACT) & x2b_ack;
+
+   assign page_hit = (r2b_raddr == bank_row) ? bank_valid : 1'b0;    // its a hit only if bank is valid
+
+   assign timer0_tc_t = ~|timer0;
+
+   assign ld_trp = (b2x_cmd == `OP_PRE) ? x2b_ack : 1'b0;
+
+   assign ld_trcd = (b2x_cmd == `OP_ACT) ? x2b_ack : 1'b0;
+   
+
+
+   always @ (*) begin
+
+       bank_prech_page_closed = 1'b0;
+       b2x_req = 1'b0;
+       b2x_cmd_t = 2'bx;
+       b2r_ack = 1'b0;
+       b2x_addr = 13'bx;
+       next_bank_st = bank_st;
+
+      case (bank_st)
+
+       `BANK_IDLE : begin
+               if(`TARGET_DESIGN == `FPGA) begin // To break the timing, b2x request are generated delayed
+                    if (~r2b_req) begin
+                       next_bank_st = `BANK_IDLE;
+                    end // if (~r2b_req)
+                    else if (page_hit) begin 
+                       b2r_ack = 1'b1;
+                       b2x_cmd_t = (r2b_write) ? `OP_WR : `OP_RD;
+                       next_bank_st = `BANK_XFR;  
+                    end // if (page_hit)
+                    else begin  // page_miss
+                       b2r_ack = 1'b1;
+                       b2x_cmd_t = `OP_PRE;
+                       next_bank_st = `BANK_PRE;  // bank was precharged on l_sdr_dma_last
+                    end // else: !if(page_hit)
+               end else begin // ASIC
+                    if (~r2b_req) begin
+                        bank_prech_page_closed = 1'b0;
+                       b2x_req = 1'b0;
+                       b2x_cmd_t = 2'bx;
+                       b2r_ack = 1'b0;
+                       b2x_addr = 13'bx;
+                       next_bank_st = `BANK_IDLE;
+                    end // if (~r2b_req)
+                    else if (page_hit) begin 
+                       b2x_req = (r2b_write) ? x2b_wrok_t & xfr_ok_t : 
+                                              x2b_rdok_t & xfr_ok_t;
+                       b2x_cmd_t = (r2b_write) ? `OP_WR : `OP_RD;
+                       b2r_ack = 1'b1;
+                       b2x_addr = r2b_caddr;
+                       next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_XFR;  // in case of hit, stay here till xfr sm acks
+                    end // if (page_hit)
+                    else begin  // page_miss
+                       b2x_req = tras_ok & x2b_pre_ok_t;
+                       b2x_cmd_t = `OP_PRE;
+                       b2r_ack = 1'b1;
+                       b2x_addr = r2b_raddr & 13'hBFF;    // Dont want to pre all banks!
+                       next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE;  // bank was precharged on l_sdr_dma_last
+                    end // else: !if(page_hit)
+               end
+       end // case: `BANK_IDLE
+
+       `BANK_PRE : begin
+          b2x_req = tras_ok & x2b_pre_ok_t;
+          b2x_cmd_t = `OP_PRE;
+          b2r_ack = 1'b0;
+          b2x_addr = l_raddr & 13'hBFF;           // Dont want to pre all banks!
+           bank_prech_page_closed = 1'b0;
+          next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE;
+       end // case: `BANK_PRE
+
+       `BANK_ACT : begin
+          b2x_req = timer0_tc & x2b_act_ok_t;
+          b2x_cmd_t = `OP_ACT;
+          b2r_ack = 1'b0;
+          b2x_addr = l_raddr;
+           bank_prech_page_closed = 1'b0;
+          next_bank_st = (x2b_ack) ? `BANK_XFR : `BANK_ACT;
+       end // case: `BANK_ACT
+       
+       `BANK_XFR : begin
+          b2x_req = (l_write) ? timer0_tc & x2b_wrok_t & xfr_ok_t :
+                    timer0_tc & x2b_rdok_t & xfr_ok_t; 
+          b2x_cmd_t = (l_write) ? `OP_WR : `OP_RD;
+          b2r_ack = 1'b0;
+          b2x_addr = l_caddr;
+           bank_prech_page_closed = 1'b0;
+          next_bank_st = (x2b_refresh) ? `BANK_ACT : 
+                          (x2b_ack & l_sdr_dma_last) ? `BANK_DMA_LAST_PRE :
+                         (x2b_ack) ? `BANK_IDLE : `BANK_XFR;
+       end // case: `BANK_XFR
+
+        `BANK_DMA_LAST_PRE : begin
+          b2x_req = tras_ok & x2b_pre_ok_t;
+          b2x_cmd_t = `OP_PRE;
+          b2r_ack = 1'b0;
+          b2x_addr = l_raddr & 13'hBFF;           // Dont want to pre all banks!
+           bank_prech_page_closed = 1'b1;
+          next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE;
+       end // case: `BANK_DMA_LAST_PRE
+          
+      endcase // case(bank_st)
+
+   end // always @ (bank_st or ...)
+
+   assign b2x_start = (bank_st == `BANK_IDLE) ? r2b_start : l_start;
+
+   assign b2x_last = (bank_st == `BANK_IDLE) ? r2b_last : l_last;
+
+   assign b2x_id = (bank_st == `BANK_IDLE) ? r2b_req_id : l_id;
+
+   assign b2x_len = (bank_st == `BANK_IDLE) ? r2b_len : l_len;
+
+   assign b2x_wrap = (bank_st == `BANK_IDLE) ? r2b_wrap : l_wrap;
+   
+endmodule // sdr_bank_fsm
diff --git a/src/peripherals/sdram/controller/sdrc_bs_convert.v b/src/peripherals/sdram/controller/sdrc_bs_convert.v
new file mode 100755 (executable)
index 0000000..dad6cf1
--- /dev/null
@@ -0,0 +1,258 @@
+/*********************************************************************
+                                                              
+  SDRAM Controller buswidth converter                                  
+                                                              
+  This file is part of the sdram controller project           
+  http://www.opencores.org/cores/sdr_ctrl/                    
+                                                              
+  Description: SDRAM Controller Buswidth converter
+
+  This module does write/read data transalation between
+     application data to SDRAM bus width
+                                                              
+  To Do:                                                      
+    nothing                                                   
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesha@opencores.org                 
+  Version  :  0.0  - 8th Jan 2012 - Initial structure
+              0.2 - 2nd Feb 2012
+                Improved the command pipe structure to accept up-to 4 command of different bank.
+             0.3 - 6th Feb 2012
+                Bug fix on read valid generation
+                                                              
+
+                                                             
+ Copyright (C) 2000 Authors and OPENCORES.ORG                
+                                                             
+ This source file may be used and distributed without         
+ restriction provided that this copyright statement is not    
+ removed from the file and that any derivative work contains  
+ the original copyright notice and the associated disclaimer. 
+                                                              
+ This source file is free software; you can redistribute it   
+ and/or modify it under the terms of the GNU Lesser General   
+ Public License as published by the Free Software Foundation; 
+ either version 2.1 of the License, or (at your option) any   
+later version.                                               
+                                                              
+ This source is distributed in the hope that it will be       
+ useful, but WITHOUT ANY WARRANTY; without even the implied   
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+ PURPOSE.  See the GNU Lesser General Public License for more 
+ details.                                                     
+                                                              
+ You should have received a copy of the GNU Lesser General    
+ Public License along with this source; if not, download it   
+ from http://www.opencores.org/lgpl.shtml                     
+                                                              
+*******************************************************************/
+
+//`include "sdrc_define.v"
+module sdrc_bs_convert (
+                    clk                 ,
+                    reset_n             ,
+                    sdr_width           ,
+
+        /* Control Signal from xfr ctrl */
+                    x2a_rdstart         ,
+                    x2a_wrstart         ,
+                    x2a_rdlast          ,
+                    x2a_wrlast          ,
+                    x2a_rddt            ,
+                    x2a_rdok            ,
+                    a2x_wrdt            ,
+                    a2x_wren_n          ,
+                    x2a_wrnext          ,
+
+   /*  Control Signal from/to to application i/f  */
+                    app_wr_data         ,
+                    app_wr_en_n         ,
+                    app_wr_next         ,
+                    app_last_wr         ,
+                    app_rd_data         ,
+                    app_rd_valid        ,
+                   app_last_rd
+               );
+
+
+`define SDR_REQ_ID_W       4
+
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W   3
+
+// B2X Command
+
+`define OP_PRE           2'b00
+`define OP_ACT           2'b01
+`define OP_RD            2'b10
+`define OP_WR            2'b11
+
+// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
+
+`define SDR_DESEL        4'b1111
+`define SDR_NOOP         4'b0111
+`define SDR_ACTIVATE     4'b0011
+`define SDR_READ         4'b0101
+`define SDR_WRITE        4'b0100
+`define SDR_BT           4'b0110
+`define SDR_PRECHARGE    4'b0010
+`define SDR_REFRESH      4'b0001
+`define SDR_MODE         4'b0000
+
+`define  ASIC            1'b1
+`define  FPGA            1'b0
+`define  TARGET_DESIGN   `ASIC
+// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
+`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
+
+parameter  APP_AW   = 30;  // Application Address Width
+parameter  APP_DW   = 64;  // Application Data Width 
+parameter  APP_BW   = 8;   // Application Byte Width
+
+parameter  SDR_DW   = 64;  // SDR Data Width 
+parameter  SDR_BW   = 8;   // SDR Byte Width
+   
+input                    clk              ;
+input                    reset_n          ;
+input [1:0]              sdr_width        ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
+
+/* Control Signal from xfr ctrl Read Transaction*/
+input                    x2a_rdstart      ; // read start indication
+input                    x2a_rdlast       ; //  read last burst access
+input [SDR_DW-1:0]       x2a_rddt         ;
+input                    x2a_rdok         ;
+
+/* Control Signal from xfr ctrl Write Transaction*/
+input                    x2a_wrstart      ; // writ start indication
+input                    x2a_wrlast       ; // write last transfer
+input                    x2a_wrnext       ;
+output [SDR_DW-1:0]      a2x_wrdt         ;
+output [SDR_BW-1:0]      a2x_wren_n       ;
+
+// Application Write Transaction
+input  [APP_DW-1:0]      app_wr_data      ;
+input  [APP_BW-1:0]      app_wr_en_n      ;
+output                   app_wr_next      ;
+output                   app_last_wr      ; // Indicate last Write Transfer for a given burst size
+
+// Application Read Transaction
+output [APP_DW-1:0]      app_rd_data      ;
+output                   app_rd_valid     ;
+output                   app_last_rd      ; // Indicate last Read Transfer for a given burst size
+
+//----------------------------------------------
+// Local Decleration
+// ----------------------------------------
+
+reg [APP_DW-1:0]         app_rd_data      ;
+reg                      app_rd_valid     ;
+reg [SDR_DW-1:0]         a2x_wrdt         ;
+reg [SDR_BW-1:0]         a2x_wren_n       ;
+reg                      app_wr_next      ;
+
+reg [23:0]               saved_rd_data    ;
+reg [1:0]                rd_xfr_count     ;
+reg [1:0]                wr_xfr_count     ;
+
+
+assign  app_last_wr = x2a_wrlast;
+assign  app_last_rd = x2a_rdlast;
+
+always @(*) begin
+        if(sdr_width == 2'b00) // 32 Bit SDR Mode
+          begin
+            a2x_wrdt             = app_wr_data;
+            a2x_wren_n           = app_wr_en_n;
+            app_wr_next          = x2a_wrnext;
+            app_rd_data          = x2a_rddt;
+            app_rd_valid         = x2a_rdok;
+          end
+        else if(sdr_width == 2'b01) // 16 Bit SDR Mode
+        begin
+           // Changed the address and length to match the 16 bit SDR Mode
+            app_wr_next          = (x2a_wrnext & wr_xfr_count[0]);
+            app_rd_valid         = (x2a_rdok & rd_xfr_count[0]);
+            if(wr_xfr_count[0] == 1'b1)
+              begin
+                a2x_wren_n      = app_wr_en_n[3:2];
+                a2x_wrdt        = app_wr_data[31:16];
+              end
+            else
+              begin
+                a2x_wren_n      = app_wr_en_n[1:0];
+                a2x_wrdt        = app_wr_data[15:0];
+              end
+            
+            app_rd_data = {x2a_rddt,saved_rd_data[15:0]};
+        end else  // 8 Bit SDR Mode
+        begin
+           // Changed the address and length to match the 16 bit SDR Mode
+            app_wr_next         = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11));
+            app_rd_valid        = (x2a_rdok &   (rd_xfr_count[1:0]== 2'b11));
+            if(wr_xfr_count[1:0] == 2'b11)
+            begin
+                a2x_wren_n      = app_wr_en_n[3];
+                a2x_wrdt        = app_wr_data[31:24];
+            end
+            else if(wr_xfr_count[1:0] == 2'b10)
+            begin
+                a2x_wren_n      = app_wr_en_n[2];
+                a2x_wrdt        = app_wr_data[23:16];
+            end
+            else if(wr_xfr_count[1:0] == 2'b01)
+            begin
+                a2x_wren_n      = app_wr_en_n[1];
+                a2x_wrdt        = app_wr_data[15:8];
+            end
+            else begin
+                a2x_wren_n      = app_wr_en_n[0];
+                a2x_wrdt        = app_wr_data[7:0];
+            end
+            
+            app_rd_data         = {x2a_rddt,saved_rd_data[23:0]};
+          end
+     end
+
+
+
+always @(posedge clk)
+  begin
+    if(!reset_n)
+      begin
+        rd_xfr_count    <= 8'b0;
+        wr_xfr_count    <= 8'b0;
+       saved_rd_data   <= 24'h0;
+      end
+    else begin
+
+       // During Write Phase
+        if(x2a_wrlast) begin
+           wr_xfr_count    <= 0;
+        end
+        else if(x2a_wrnext) begin
+           wr_xfr_count <= wr_xfr_count + 1'b1;
+        end
+
+       // During Read Phase
+        if(x2a_rdlast) begin
+           rd_xfr_count    <= 0;
+        end
+        else if(x2a_rdok) begin
+           rd_xfr_count   <= rd_xfr_count + 1'b1;
+       end
+
+       // Save Previous Data
+        if(x2a_rdok) begin
+          if(sdr_width == 2'b01) // 16 Bit SDR Mode
+             saved_rd_data[15:0]  <= x2a_rddt;
+            else begin// 8 bit SDR Mode - 
+              if(rd_xfr_count[1:0] == 2'b00)      saved_rd_data[7:0]   <= x2a_rddt[7:0];
+              else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8]  <= x2a_rddt[7:0];
+              else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0];
+           end
+        end
+    end
+end
+
+endmodule // sdr_bs_convert
diff --git a/src/peripherals/sdram/controller/sdrc_core.v b/src/peripherals/sdram/controller/sdrc_core.v
new file mode 100755 (executable)
index 0000000..8a0e495
--- /dev/null
@@ -0,0 +1,508 @@
+/*********************************************************************
+                                                              
+  SDRAM Controller Core File                                  
+                                                              
+  This file is part of the sdram controller project           
+  http://www.opencores.org/cores/sdr_ctrl/                    
+                                                              
+  Description: SDRAM Controller Core Module
+    2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank.
+    This block integrate following sub modules
+
+    sdrc_bs_convert   
+        convert the system side 32 bit into equvailent 8/16/32 SDR format
+    sdrc_req_gen    
+        This module takes requests from the app, chops them to burst booundaries
+        if wrap=0, decodes the bank and passe the request to bank_ctl
+   sdrc_xfr_ctl
+      This module takes requests from sdr_bank_ctl, runs the transfer and
+      controls data flow to/from the app. At the end of the transfer it issues a
+      burst terminate if not at the end of a burst and another command to this
+      bank is not available.
+
+   sdrc_bank_ctl
+      This module takes requests from sdr_req_gen, checks for page hit/miss and
+      issues precharge/activate commands and then passes the request to
+      sdr_xfr_ctl. 
+
+
+  Assumption: SDRAM Pads should be placed near to this module. else
+  user should add a FF near the pads
+                                                              
+  To Do:                                                      
+    nothing                                                   
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesha@opencores.org                 
+  Version  : 0.0 - 8th Jan 2012
+                Initial version with 16/32 Bit SDRAM Support
+           : 0.1 - 24th Jan 2012
+                8 Bit SDRAM Support is added
+             0.2 - 2nd Feb 2012
+                  Improved the command pipe structure to accept up-to 
+                  4 command of different bank.
+            0.3 - 7th Feb 2012
+                  Bug fix for parameter defination for request length has changed from 9 to 12
+             0.4 - 26th April 2013
+                   SDRAM Address Bit is Extended by 12 bit to 13 bit to support higher SDRAM
+
+                                                             
+ Copyright (C) 2000 Authors and OPENCORES.ORG                
+                                                             
+ This source file may be used and distributed without         
+ restriction provided that this copyright statement is not    
+ removed from the file and that any derivative work contains  
+ the original copyright notice and the associated disclaimer. 
+                                                              
+ This source file is free software; you can redistribute it   
+ and/or modify it under the terms of the GNU Lesser General   
+ Public License as published by the Free Software Foundation; 
+ either version 2.1 of the License, or (at your option) any   
+later version.                                               
+                                                              
+ This source is distributed in the hope that it will be       
+ useful, but WITHOUT ANY WARRANTY; without even the implied   
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+ PURPOSE.  See the GNU Lesser General Public License for more 
+ details.                                                     
+                                                              
+ You should have received a copy of the GNU Lesser General    
+ Public License along with this source; if not, download it   
+ from http://www.opencores.org/lgpl.shtml                     
+                                                              
+*******************************************************************/
+
+
+
+module sdrc_core 
+           (
+               clk,
+                pad_clk,
+               reset_n,
+                sdr_width,
+               cfg_colbits,
+
+               /* Request from app */
+               app_req,                // Transfer Request
+               app_req_addr,           // SDRAM Address
+               app_req_len,            // Burst Length (in 16 bit words)
+               app_req_wrap,           // Wrap mode request (xfr_len = 4)
+               app_req_wr_n,           // 0 => Write request, 1 => read req
+               app_req_ack,            // Request has been accepted
+               cfg_req_depth,          //how many req. buffer should hold
+               
+               app_wr_data,
+                app_wr_en_n,
+               app_last_wr,
+
+               app_rd_data,
+               app_rd_valid,
+               app_last_rd,
+               app_wr_next_req,
+               sdr_init_done,
+               app_req_dma_last,
+
+               /* Interface to SDRAMs */
+               sdr_cs_n,
+               sdr_cke,
+               sdr_ras_n,
+               sdr_cas_n,
+               sdr_we_n,
+               sdr_dqm,
+               sdr_ba,
+               sdr_addr, 
+               pad_sdr_din,
+               sdr_dout,
+               sdr_den_n,
+
+               /* Parameters */
+               cfg_sdr_en,
+               cfg_sdr_mode_reg,
+               cfg_sdr_tras_d,
+               cfg_sdr_trp_d,
+               cfg_sdr_trcd_d,
+               cfg_sdr_cas,
+               cfg_sdr_trcar_d,
+               cfg_sdr_twr_d,
+               cfg_sdr_rfsh,
+               cfg_sdr_rfmax);
+
+
+`define SDR_REQ_ID_W       4
+
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W   3
+
+// B2X Command
+
+`define OP_PRE           2'b00
+`define OP_ACT           2'b01
+`define OP_RD            2'b10
+`define OP_WR            2'b11
+
+// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
+
+`define SDR_DESEL        4'b1111
+`define SDR_NOOP         4'b0111
+`define SDR_ACTIVATE     4'b0011
+`define SDR_READ         4'b0101
+`define SDR_WRITE        4'b0100
+`define SDR_BT           4'b0110
+`define SDR_PRECHARGE    4'b0010
+`define SDR_REFRESH      4'b0001
+`define SDR_MODE         4'b0000
+
+`define  ASIC            1'b1
+`define  FPGA            1'b0
+`define  TARGET_DESIGN   `ASIC
+// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
+`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
+  
+parameter  APP_AW   = 26;  // Application Address Width
+parameter  APP_DW   = 64;  // Application Data Width 
+parameter  APP_BW   = 8;   // Application Byte Width
+parameter  APP_RW   = 9;   // Application Request Width
+
+parameter  SDR_DW   = 64;  // SDR Data Width 
+parameter  SDR_BW   = 8;   // SDR Byte Width
+             
+
+//-----------------------------------------------
+// Global Variable
+// ----------------------------------------------
+input                   clk                 ; // SDRAM Clock 
+input                   pad_clk             ; // SDRAM Clock from Pad, used for registering Read Data
+input                   reset_n             ; // Reset Signal
+input [1:0]             sdr_width           ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
+input [1:0]             cfg_colbits         ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
+
+
+//------------------------------------------------
+// Request from app
+//------------------------------------------------
+input                  app_req             ; // Application Request
+input [APP_AW-1:0]     app_req_addr        ; // Address 
+input                  app_req_wr_n        ; // 0 - Write, 1 - Read
+input                   app_req_wrap        ; // Address Wrap
+output                  app_req_ack         ; // Application Request Ack
+               
+input [APP_DW-1:0]     app_wr_data         ; // Write Data
+output                         app_wr_next_req     ; // Next Write Data Request
+input [APP_BW-1:0]     app_wr_en_n         ; // Byte wise Write Enable
+output                  app_last_wr         ; // Last Write trannsfer of a given Burst
+output [APP_DW-1:0]    app_rd_data         ; // Read Data
+output                  app_rd_valid        ; // Read Valid
+output                  app_last_rd         ; // Last Read Transfer of a given Burst
+               
+//------------------------------------------------
+// Interface to SDRAMs
+//------------------------------------------------
+output                  sdr_cke             ; // SDRAM CKE
+output                         sdr_cs_n            ; // SDRAM Chip Select
+output                  sdr_ras_n           ; // SDRAM ras
+output                  sdr_cas_n           ; // SDRAM cas
+output                 sdr_we_n            ; // SDRAM write enable
+output [SDR_BW-1:0]    sdr_dqm             ; // SDRAM Data Mask
+output [1:0]           sdr_ba              ; // SDRAM Bank Enable
+output [12:0]          sdr_addr            ; // SDRAM Address
+input [SDR_DW-1:0]     pad_sdr_din         ; // SDRA Data Input
+output [SDR_DW-1:0]    sdr_dout            ; // SDRAM Data Output
+output [SDR_BW-1:0]    sdr_den_n           ; // SDRAM Data Output enable
+
+//------------------------------------------------
+// Configuration Parameter
+//------------------------------------------------
+output                  sdr_init_done       ; // Indicate SDRAM Initialisation Done
+input [3:0]            cfg_sdr_tras_d      ; // Active to precharge delay
+input [3:0]             cfg_sdr_trp_d       ; // Precharge to active delay
+input [3:0]             cfg_sdr_trcd_d      ; // Active to R/W delay
+input                  cfg_sdr_en          ; // Enable SDRAM controller
+input [1:0]            cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
+input [APP_RW-1:0]     app_req_len         ; // Application Burst Request length in 32 bit 
+input [12:0]           cfg_sdr_mode_reg    ;
+input [2:0]            cfg_sdr_cas         ; // SDRAM CAS Latency
+input [3:0]            cfg_sdr_trcar_d     ; // Auto-refresh period
+input [3:0]             cfg_sdr_twr_d       ; // Write recovery delay
+input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh;
+input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
+input                   app_req_dma_last;    // this signal should close the bank
+
+/****************************************************************************/
+// Internal Nets
+   
+// SDR_REQ_GEN
+wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
+wire [1:0]             r2b_ba;
+wire [12:0]            r2b_raddr;
+wire [12:0]            r2b_caddr;
+wire [`REQ_BW-1:0]     r2b_len;
+
+// SDR BANK CTL
+wire [`SDR_REQ_ID_W-1:0]b2x_id;
+wire [1:0]             b2x_ba;
+wire [12:0]            b2x_addr;
+wire [`REQ_BW-1:0]     b2x_len;
+wire [1:0]             b2x_cmd;
+
+// SDR_XFR_CTL
+wire [3:0]             x2b_pre_ok;
+wire [`SDR_REQ_ID_W-1:0]xfr_id;
+wire [APP_DW-1:0]      app_rd_data;
+wire                   sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n; 
+wire [SDR_BW-1:0]      sdr_dqm;
+wire [1:0]             sdr_ba;
+wire [12:0]            sdr_addr;
+wire [SDR_DW-1:0]      sdr_dout;
+wire [SDR_DW-1:0]      sdr_dout_int;
+wire [SDR_BW-1:0]      sdr_den_n;
+wire [SDR_BW-1:0]      sdr_den_n_int;
+
+wire [1:0]             xfr_bank_sel;
+
+wire [APP_AW-1:0]        app_req_addr;
+wire [APP_RW-1:0]        app_req_len;
+
+wire [APP_DW-1:0]        app_wr_data;
+wire [SDR_DW-1:0]        a2x_wrdt       ;
+wire [APP_BW-1:0]        app_wr_en_n;
+wire [SDR_BW-1:0]        a2x_wren_n;
+
+//wire [31:0] app_rd_data;
+wire [SDR_DW-1:0]        x2a_rddt;
+
+
+// synopsys translate_off 
+   wire [3:0]           sdr_cmd;
+   assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n}; 
+// synopsys translate_on 
+
+assign sdr_den_n = sdr_den_n_int ; 
+assign sdr_dout  = sdr_dout_int ;
+
+
+// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
+// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
+// register w.r.t pad sdram clk
+reg [SDR_DW-1:0] pad_sdr_din1;
+reg [SDR_DW-1:0] pad_sdr_din2;
+always@(posedge pad_clk) begin
+   pad_sdr_din1 <= pad_sdr_din;
+end
+
+always@(posedge clk) begin
+   pad_sdr_din2 <= pad_sdr_din1;
+end
+
+
+   /****************************************************************************/
+   // Instantiate sdr_req_gen
+   // This module takes requests from the app, chops them to burst booundaries
+   // if wrap=0, decodes the bank and passe the request to bank_ctl
+
+sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen (
+          .clk                (clk          ),
+          .reset_n            (reset_n            ),
+         .cfg_colbits        (cfg_colbits        ),
+          .sdr_width          (sdr_width          ),
+
+       /* Req to xfr_ctl */
+          .r2x_idle           (r2x_idle           ),
+
+       /* Request from app */
+          .req                (app_req            ),
+          .req_id             (4'b0               ),
+          .req_addr           (app_req_addr       ),
+          .req_len            (app_req_len        ),
+          .req_wrap           (app_req_wrap       ),
+          .req_wr_n           (app_req_wr_n       ),
+          .req_ack            (app_req_ack        ),
+               
+       /* Req to bank_ctl */
+          .r2b_req            (r2b_req            ),
+          .r2b_req_id         (r2b_req_id         ),
+          .r2b_start          (r2b_start          ),
+          .r2b_last           (r2b_last           ),
+          .r2b_wrap           (r2b_wrap           ),
+          .r2b_ba             (r2b_ba             ),
+          .r2b_raddr          (r2b_raddr          ),
+          .r2b_caddr          (r2b_caddr          ),
+          .r2b_len            (r2b_len            ),
+          .r2b_write          (r2b_write          ),
+          .b2r_ack            (b2r_ack            ),
+          .b2r_arb_ok         (b2r_arb_ok         )
+     );
+
+   /****************************************************************************/
+   // Instantiate sdr_bank_ctl
+   // This module takes requests from sdr_req_gen, checks for page hit/miss and
+   // issues precharge/activate commands and then passes the request to
+   // sdr_xfr_ctl. 
+
+sdrc_bank_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bank_ctl (
+          .clk                (clk          ),
+          .reset_n            (reset_n            ),
+          .a2b_req_depth      (cfg_req_depth      ),
+                             
+      /* Req from req_gen */
+          .r2b_req            (r2b_req            ),
+          .r2b_req_id         (r2b_req_id         ),
+          .r2b_start          (r2b_start          ),
+          .r2b_last           (r2b_last           ),
+          .r2b_wrap           (r2b_wrap           ),
+          .r2b_ba             (r2b_ba             ),
+          .r2b_raddr          (r2b_raddr          ),
+          .r2b_caddr          (r2b_caddr          ),
+          .r2b_len            (r2b_len            ),
+          .r2b_write          (r2b_write          ),
+          .b2r_arb_ok         (b2r_arb_ok         ),
+          .b2r_ack            (b2r_ack            ),
+                             
+      /* Transfer request to xfr_ctl */
+          .b2x_idle           (b2x_idle           ),
+          .b2x_req            (b2x_req            ),
+          .b2x_start          (b2x_start          ),
+          .b2x_last           (b2x_last           ),
+          .b2x_wrap           (b2x_wrap           ),
+          .b2x_id             (b2x_id             ),
+          .b2x_ba             (b2x_ba             ),
+          .b2x_addr           (b2x_addr           ),
+          .b2x_len            (b2x_len            ),
+          .b2x_cmd            (b2x_cmd            ),
+          .x2b_ack            (x2b_ack            ),
+                    
+      /* Status from xfr_ctl */
+          .b2x_tras_ok        (b2x_tras_ok        ),
+          .x2b_refresh        (x2b_refresh        ),
+          .x2b_pre_ok         (x2b_pre_ok         ),
+          .x2b_act_ok         (x2b_act_ok         ),
+          .x2b_rdok           (x2b_rdok           ),
+          .x2b_wrok           (x2b_wrok           ),
+
+      /* for generate cuurent xfr address msb */
+          .sdr_req_norm_dma_last(app_req_dma_last),
+          .xfr_bank_sel       (xfr_bank_sel       ),
+
+       /* SDRAM Timing */
+          .tras_delay         (cfg_sdr_tras_d     ),
+          .trp_delay          (cfg_sdr_trp_d      ),
+          .trcd_delay         (cfg_sdr_trcd_d     )
+      );
+   
+   /****************************************************************************/
+   // Instantiate sdr_xfr_ctl
+   // This module takes requests from sdr_bank_ctl, runs the transfer and
+   // controls data flow to/from the app. At the end of the transfer it issues a
+   // burst terminate if not at the end of a burst and another command to this
+   // bank is not available.
+
+sdrc_xfr_ctl #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_xfr_ctl (
+          .clk                (clk          ),
+          .reset_n            (reset_n            ),
+                           
+      /* Transfer request from bank_ctl */
+          .r2x_idle           (r2x_idle           ),
+          .b2x_idle           (b2x_idle           ),
+          .b2x_req            (b2x_req            ),
+          .b2x_start          (b2x_start          ),
+          .b2x_last           (b2x_last           ),
+          .b2x_wrap           (b2x_wrap           ),
+          .b2x_id             (b2x_id             ),
+          .b2x_ba             (b2x_ba             ),
+          .b2x_addr           (b2x_addr           ),
+          .b2x_len            (b2x_len            ),
+          .b2x_cmd            (b2x_cmd            ),
+          .x2b_ack            (x2b_ack            ),
+                    
+       /* Status to bank_ctl, req_gen */
+          .b2x_tras_ok        (b2x_tras_ok        ),
+          .x2b_refresh        (x2b_refresh        ),
+          .x2b_pre_ok         (x2b_pre_ok         ),
+          .x2b_act_ok         (x2b_act_ok         ),
+          .x2b_rdok           (x2b_rdok           ),
+          .x2b_wrok           (x2b_wrok           ),
+                   
+       /* SDRAM I/O */
+          .sdr_cs_n           (sdr_cs_n           ),
+          .sdr_cke            (sdr_cke            ),
+          .sdr_ras_n          (sdr_ras_n          ),
+          .sdr_cas_n          (sdr_cas_n          ),
+          .sdr_we_n           (sdr_we_n           ),
+          .sdr_dqm            (sdr_dqm            ),
+          .sdr_ba             (sdr_ba             ),
+          .sdr_addr           (sdr_addr           ),
+          .sdr_din            (pad_sdr_din2       ),
+          .sdr_dout           (sdr_dout_int       ),
+          .sdr_den_n          (sdr_den_n_int      ),
+      /* Data Flow to the app */
+          .x2a_rdstart        (x2a_rdstart        ),
+          .x2a_wrstart        (x2a_wrstart        ),
+          .x2a_id             (xfr_id             ),
+          .x2a_rdlast         (x2a_rdlast         ),
+          .x2a_wrlast         (x2a_wrlast         ),
+          .a2x_wrdt           (a2x_wrdt           ),
+          .a2x_wren_n         (a2x_wren_n         ),
+          .x2a_wrnext         (x2a_wrnext         ),
+          .x2a_rddt           (x2a_rddt           ),
+          .x2a_rdok           (x2a_rdok           ),
+          .sdr_init_done      (sdr_init_done      ),
+                           
+      /* SDRAM Parameters */
+          .sdram_enable       (cfg_sdr_en         ),
+          .sdram_mode_reg     (cfg_sdr_mode_reg   ),
+                   
+      /* current xfr bank */
+          .xfr_bank_sel       (xfr_bank_sel       ),
+
+      /* SDRAM Timing */
+          .cas_latency        (cfg_sdr_cas        ),
+          .trp_delay          (cfg_sdr_trp_d      ),
+          .trcar_delay        (cfg_sdr_trcar_d    ),
+          .twr_delay          (cfg_sdr_twr_d      ),
+          .rfsh_time          (cfg_sdr_rfsh       ),
+          .rfsh_rmax          (cfg_sdr_rfmax      )
+    );
+   
+   /****************************************************************************/
+   // Instantiate sdr_bs_convert
+   //    This model handle the bus with transaltion from application layer to
+   //       8/16/32 SDRAM Memory format
+   //     During Write Phase, this block split the data as per SDRAM Width
+   //     During Read Phase, This block does the re-packing based on SDRAM
+   //     Width
+   //---------------------------------------------------------------------------
+sdrc_bs_convert #(.SDR_DW(SDR_DW) ,  .SDR_BW(SDR_BW)) u_bs_convert (
+          .clk                (clk          ),
+          .reset_n            (reset_n            ),
+          .sdr_width          (sdr_width          ),
+
+   /* Control Signal from xfr ctrl */
+          // Read Interface Inputs
+          .x2a_rdstart        (x2a_rdstart        ),
+          .x2a_rdlast         (x2a_rdlast         ),
+          .x2a_rdok           (x2a_rdok           ),
+         // Read Interface outputs
+          .x2a_rddt           (x2a_rddt           ),
+
+          // Write Interface, Inputs
+          .x2a_wrstart        (x2a_wrstart        ),
+          .x2a_wrlast         (x2a_wrlast         ),
+          .x2a_wrnext         (x2a_wrnext         ),
+
+          // Write Interface, Outputs
+          .a2x_wrdt           (a2x_wrdt           ),
+          .a2x_wren_n         (a2x_wren_n         ),
+
+   /* Control Signal from sdrc_bank_ctl  */
+
+   /*  Control Signal from/to to application i/f  */
+          .app_wr_data        (app_wr_data        ),
+          .app_wr_en_n        (app_wr_en_n        ),
+          .app_wr_next        (app_wr_next_req    ),
+         .app_last_wr        (app_last_wr        ),
+          .app_rd_data        (app_rd_data        ),
+          .app_rd_valid       (app_rd_valid       ),
+         .app_last_rd        (app_last_rd        )
+
+       );   
+   
+endmodule // sdrc_core
diff --git a/src/peripherals/sdram/controller/sdrc_req_gen.v b/src/peripherals/sdram/controller/sdrc_req_gen.v
new file mode 100755 (executable)
index 0000000..9ca80db
--- /dev/null
@@ -0,0 +1,371 @@
+/*********************************************************************
+                                                              
+  SDRAM Controller Request Generation                                  
+                                                              
+  This file is part of the sdram controller project           
+  http://www.opencores.org/cores/sdr_ctrl/                    
+                                                              
+  Description: SDRAM Controller Reguest Generation
+
+  Address Generation Based on cfg_colbits
+     cfg_colbits= 2'b00
+            Address[7:0]    - Column Address
+            Address[9:8]    - Bank Address
+            Address[22:10]  - Row Address
+     cfg_colbits= 2'b01
+            Address[8:0]    - Column Address
+            Address[10:9]   - Bank Address
+            Address[23:11]  - Row Address
+     cfg_colbits= 2'b10
+            Address[9:0]    - Column Address
+            Address[11:10]   - Bank Address
+            Address[24:12]  - Row Address
+     cfg_colbits= 2'b11
+            Address[10:0]    - Column Address
+            Address[12:11]   - Bank Address
+            Address[25:13]  - Row Address
+
+  The SDRAMs are operated in 4 beat burst mode.
+
+  If Wrap = 0; 
+      If the current burst cross the page boundary, then this block split the request 
+      into two coressponding change in address and request length
+
+  if the current burst cross the page boundar.
+  This module takes requests from the memory controller, 
+  chops them to page boundaries if wrap=0, 
+  and passes the request to bank_ctl
+
+  Note: With Wrap = 0, each request from Application layer will be splited into two request, 
+       if the current burst cross the page boundary. 
+
+  To Do:                                                      
+    nothing                                                   
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesha@opencores.org                 
+  Version  : 0.0 - 8th Jan 2012
+             0.1 - 5th Feb 2012, column/row/bank address are register to improve the timing issue in FPGA synthesis
+                                                              
+
+                                                             
+ Copyright (C) 2000 Authors and OPENCORES.ORG                
+                                                             
+ This source file may be used and distributed without         
+ restriction provided that this copyright statement is not    
+ removed from the file and that any derivative work contains  
+ the original copyright notice and the associated disclaimer. 
+                                                              
+ This source file is free software; you can redistribute it   
+ and/or modify it under the terms of the GNU Lesser General   
+ Public License as published by the Free Software Foundation; 
+ either version 2.1 of the License, or (at your option) any   
+later version.                                               
+                                                              
+ This source is distributed in the hope that it will be       
+ useful, but WITHOUT ANY WARRANTY; without even the implied   
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+ PURPOSE.  See the GNU Lesser General Public License for more 
+ details.                                                     
+                                                              
+ You should have received a copy of the GNU Lesser General    
+ Public License along with this source; if not, download it   
+ from http://www.opencores.org/lgpl.shtml                     
+                                                              
+*******************************************************************/
+
+
+
+module sdrc_req_gen (clk,
+                   reset_n,
+                   cfg_colbits,
+                   sdr_width,
+
+                   /* Request from app */
+                   req,                // Transfer Request
+                   req_id,             // ID for this transfer
+                   req_addr,           // SDRAM Address
+                   req_len,            // Burst Length (in 32 bit words)
+                   req_wrap,           // Wrap mode request (xfr_len = 4)
+                   req_wr_n,           // 0 => Write request, 1 => read req
+                   req_ack,            // Request has been accepted
+                   
+                   /* Req to xfr_ctl */
+                   r2x_idle,
+
+                   /* Req to bank_ctl */
+                   r2b_req,            // request
+                   r2b_req_id,         // ID
+                   r2b_start,          // First chunk of burst
+                   r2b_last,           // Last chunk of burst
+                   r2b_wrap,           // Wrap Mode
+                   r2b_ba,             // bank address
+                   r2b_raddr,          // row address
+                   r2b_caddr,          // col address
+                   r2b_len,            // length
+                   r2b_write,          // write request
+                   b2r_ack,
+                   b2r_arb_ok
+                   );
+
+
+`define SDR_REQ_ID_W       4
+
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W   3
+
+// B2X Command
+
+`define OP_PRE           2'b00
+`define OP_ACT           2'b01
+`define OP_RD            2'b10
+`define OP_WR            2'b11
+
+// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
+
+`define SDR_DESEL        4'b1111
+`define SDR_NOOP         4'b0111
+`define SDR_ACTIVATE     4'b0011
+`define SDR_READ         4'b0101
+`define SDR_WRITE        4'b0100
+`define SDR_BT           4'b0110
+`define SDR_PRECHARGE    4'b0010
+`define SDR_REFRESH      4'b0001
+`define SDR_MODE         4'b0000
+
+`define  ASIC            1'b1
+`define  FPGA            1'b0
+`define  TARGET_DESIGN   `ASIC
+// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
+`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
+
+parameter  APP_AW   = 26;  // Application Address Width
+parameter  APP_DW   = 64;  // Application Data Width 
+parameter  APP_BW   = 8;   // Application Byte Width
+parameter  APP_RW   = 9;   // Application Request Width
+
+parameter  SDR_DW   = 64;  // SDR Data Width 
+parameter  SDR_BW   = 8;   // SDR Byte Width
+
+
+input                   clk           ;
+input                   reset_n       ;
+input [1:0]             cfg_colbits   ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
+
+/* Request from app */
+input                  req           ; // Request 
+input [`SDR_REQ_ID_W-1:0] req_id      ; // Request ID
+input [APP_AW-1:0]     req_addr      ; // Request Address
+input [APP_RW-1:0]     req_len       ; // Request length
+input                  req_wr_n      ; // 0 -Write, 1 - Read
+input                   req_wrap      ; // 1 - Wrap the Address on page boundary
+output                         req_ack       ; // Request Ack
+               
+/* Req to bank_ctl */
+output                         r2x_idle      ; 
+output                  r2b_req       ; // Request
+output                  r2b_start     ; // First Junk of the Burst Access
+output                  r2b_last      ; // Last Junk of the Burst Access
+output                  r2b_write     ; // 1 - Write, 0 - Read
+output                  r2b_wrap      ; // 1 - Wrap the Address at the page boundary.
+output [`SDR_REQ_ID_W-1:0]     r2b_req_id;
+output [1:0]           r2b_ba        ; // Bank Address
+output [12:0]          r2b_raddr     ; // Row Address
+output [12:0]          r2b_caddr     ; // Column Address
+output [`REQ_BW-1:0]   r2b_len       ; // Burst Length
+input                  b2r_ack       ; // Request Ack
+input                   b2r_arb_ok    ; // Bank controller fifo is not full and ready to accept the command
+//
+input [1:0]            sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit
+                                         
+
+   /****************************************************************************/
+   // Internal Nets
+
+   `define REQ_IDLE        2'b00
+   `define REQ_ACTIVE      2'b01
+   `define REQ_PAGE_WRAP   2'b10
+
+   reg  [1:0]          req_st, next_req_st;
+   reg                         r2x_idle, req_ack, r2b_req, r2b_start, 
+                       r2b_write, req_idle, req_ld, lcl_wrap;
+   reg [`SDR_REQ_ID_W-1:0]     r2b_req_id;
+   reg [`REQ_BW-1:0]   lcl_req_len;
+
+   wire                r2b_last, page_ovflw;
+   reg page_ovflw_r;
+   wire [`REQ_BW-1:0]  r2b_len, next_req_len;
+   wire [12:0]                 max_r2b_len;
+   reg  [12:0]                 max_r2b_len_r;
+
+   reg [1:0]           r2b_ba;
+   reg [12:0]          r2b_raddr;
+   reg [12:0]          r2b_caddr;
+
+   reg [APP_AW-1:0]    curr_sdr_addr ;
+   wire [APP_AW-1:0]   next_sdr_addr ;
+
+
+//--------------------------------------------------------------------
+// Generate the internal Adress and Burst length Based on sdram width
+//--------------------------------------------------------------------
+reg [APP_AW:0]           req_addr_int;
+reg [APP_RW-1:0]         req_len_int;
+
+always @(*) begin
+   if(sdr_width == 2'b00) begin // 32 Bit SDR Mode
+      req_addr_int     = {1'b0,req_addr};
+      req_len_int      = req_len;
+   end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode
+      // Changed the address and length to match the 16 bit SDR Mode
+      req_addr_int     = {req_addr,1'b0};
+      req_len_int      = {req_len,1'b0};
+   end else  begin // 8 Bit SDR Mode
+      // Changed the address and length to match the 16 bit SDR Mode
+      req_addr_int    = {req_addr,2'b0};
+      req_len_int     = {req_len,2'b0};
+   end
+end
+
+   //
+   // Identify the page over flow.
+   // Find the Maximum Burst length allowed from the selected column
+   // address, If the requested burst length is more than the allowed Maximum
+   // burst length, then we need to handle the bank cross over case and we
+   // need to split the reuest.
+   //
+   assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - {4'b0, req_addr_int[7:0]}) :
+                       (cfg_colbits == 2'b01) ? (12'h200 - {3'b0, req_addr_int[8:0]}) :
+                       (cfg_colbits == 2'b10) ? (12'h400 - {2'b0, req_addr_int[9:0]}) : (12'h800 - {1'b0, req_addr_int[10:0]});
+
+
+     // If the wrap = 0 and current application burst length is crossing the page boundary, 
+     // then request will be split into two with corresponding change in request address and request length.
+     //
+     // If the wrap = 0 and current burst length is not crossing the page boundary, 
+     // then request from application layer will be transparently passed on the bank control block.
+
+     //
+     // if the wrap = 1, then this block will not modify the request address and length. 
+     // The wrapping functionality will be handle by the bank control module and 
+     // column address will rewind back as follows XX -> FF ? 00 ? 1
+     //
+     // Note: With Wrap = 0, each request from Application layer will be spilited into two request, 
+     //        if the current burst cross the page boundary. 
+   assign page_ovflw = ({1'b0, req_len_int} > max_r2b_len) ? (req_ack && ~req_wrap) : 1'b0; // vish change
+
+   assign r2b_len = r2b_start ? ((page_ovflw_r) ? max_r2b_len_r : lcl_req_len) :
+                      lcl_req_len;
+
+   assign next_req_len = lcl_req_len - r2b_len;
+
+   assign next_sdr_addr = curr_sdr_addr + r2b_len;
+
+
+   assign r2b_wrap = lcl_wrap;
+
+   assign r2b_last = (r2b_start & !page_ovflw_r) | (req_st == `REQ_PAGE_WRAP);
+//
+//
+//
+   always @ (posedge clk) begin
+
+      page_ovflw_r   <= (req_ack) ? page_ovflw: 'h0;
+
+      max_r2b_len_r  <= (req_ack) ? max_r2b_len: 'h0;
+      r2b_start      <= (req_ack) ? 1'b1 :
+                       (b2r_ack) ? 1'b0 : r2b_start;
+
+      r2b_write      <= (req_ack) ? ~req_wr_n : r2b_write;
+
+      r2b_req_id     <= (req_ack) ? req_id : r2b_req_id;
+
+      lcl_wrap       <= (req_ack) ? req_wrap : lcl_wrap;
+            
+      lcl_req_len    <= (req_ack) ? req_len_int  :
+                       (req_ld) ? next_req_len : lcl_req_len;
+
+      curr_sdr_addr  <= (req_ack) ? req_addr_int :
+                       (req_ld) ? next_sdr_addr : curr_sdr_addr;
+
+   end // always @ (posedge clk)
+   
+   always @ (*) begin
+      r2x_idle    = 1'b0;
+      req_idle    = 1'b0;
+      req_ack     = 1'b0;
+      req_ld      = 1'b0;
+      r2b_req     = 1'b0;
+      next_req_st = `REQ_IDLE;
+
+      case (req_st)      // synopsys full_case parallel_case
+
+       `REQ_IDLE : begin
+          r2x_idle = ~req;
+          req_idle = 1'b1;
+          req_ack = req & b2r_arb_ok;
+          req_ld = 1'b0;
+          r2b_req = 1'b0;
+          next_req_st = (req & b2r_arb_ok) ? `REQ_ACTIVE : `REQ_IDLE;
+       end // case: `REQ_IDLE
+
+       `REQ_ACTIVE : begin
+          r2x_idle = 1'b0;
+          req_idle = 1'b0;
+          req_ack = 1'b0;
+          req_ld = b2r_ack;
+          r2b_req = 1'b1;                       // req_gen to bank_req
+          next_req_st = (b2r_ack ) ? ((page_ovflw_r) ? `REQ_PAGE_WRAP :`REQ_IDLE) : `REQ_ACTIVE;
+       end // case: `REQ_ACTIVE
+       `REQ_PAGE_WRAP : begin
+          r2x_idle = 1'b0;
+          req_idle = 1'b0;
+          req_ack  = 1'b0;
+          req_ld = b2r_ack;
+          r2b_req = 1'b1;                       // req_gen to bank_req
+          next_req_st = (b2r_ack) ? `REQ_IDLE : `REQ_PAGE_WRAP;
+       end // case: `REQ_ACTIVE
+
+      endcase // case(req_st)
+
+   end // always @ (req_st or ....)
+
+   always @ (posedge clk)
+      if (~reset_n) begin
+        req_st <= `REQ_IDLE;
+      end // if (~reset_n)
+      else begin
+        req_st <= next_req_st;
+      end // else: !if(~reset_n)
+//
+// addrs bits for the bank, row and column
+//
+// Register row/column/bank to improve fpga timing issue
+wire [APP_AW-1:0]      map_address ;
+
+assign      map_address  = (req_ack) ? req_addr_int :
+                          (req_ld)  ? next_sdr_addr : curr_sdr_addr;
+
+always @ (posedge clk) begin
+// Bank Bits are always - 2 Bits
+    r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]}   :
+             (cfg_colbits == 2'b01) ? {map_address[10:9]}  :
+             (cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11];
+
+/********************
+*  Colbits Mapping:
+*           2'b00 - 8 Bit
+*           2'b01 - 16 Bit
+*           2'b10 - 10 Bit
+*           2'b11 - 11 Bits
+************************/
+    r2b_caddr <= (cfg_colbits == 2'b00) ? {5'b0, map_address[7:0]} :
+                (cfg_colbits == 2'b01) ? {4'b0, map_address[8:0]} :
+                (cfg_colbits == 2'b10) ? {3'b0, map_address[9:0]} : {2'b0, map_address[10:0]};
+
+    r2b_raddr <= (cfg_colbits == 2'b00)  ? map_address[22:10] :
+                (cfg_colbits == 2'b01)  ? map_address[23:11] :
+                (cfg_colbits == 2'b10)  ? map_address[24:12] : map_address[25:13];
+end       
+   
+endmodule // sdr_req_gen
diff --git a/src/peripherals/sdram/controller/sdrc_top.v b/src/peripherals/sdram/controller/sdrc_top.v
new file mode 100755 (executable)
index 0000000..fc2e032
--- /dev/null
@@ -0,0 +1,325 @@
+/*********************************************************************
+                                                              
+  SDRAM Controller top File                                  
+                                                              
+  This file is part of the sdram controller project           
+  http://www.opencores.org/cores/sdr_ctrl/                    
+                                                              
+  Description: SDRAM Controller Top Module.
+    Support 81/6/32 Bit SDRAM.
+    Column Address is Programmable
+    Bank Bit are 2 Bit
+    Row Bits are 12 Bits
+
+    This block integrate following sub modules
+
+    sdrc_core   
+        SDRAM Controller file
+    wb2sdrc    
+        This module transalate the bus protocl from wishbone to custome
+       sdram controller
+                                                              
+  To Do:                                                      
+    nothing                                                   
+                                                              
+  Author(s): Dinesh Annayya, dinesha@opencores.org                 
+  Version  : 0.0 - 8th Jan 2012
+                Initial version with 16/32 Bit SDRAM Support
+           : 0.1 - 24th Jan 2012
+                8 Bit SDRAM Support is added
+            0.2 - 31st Jan 2012
+                sdram_dq and sdram_pad_clk are internally generated
+            0.3 - 26th April 2013
+                  Sdram Address witdh is increased from 12 to 13bits
+
+                                                             
+ Copyright (C) 2000 Authors and OPENCORES.ORG                
+                                                             
+ This source file may be used and distributed without         
+ restriction provided that this copyright statement is not    
+ removed from the file and that any derivative work contains  
+ the original copyright notice and the associated disclaimer. 
+                                                              
+ This source file is free software; you can redistribute it   
+ and/or modify it under the terms of the GNU Lesser General   
+ Public License as published by the Free Software Foundation; 
+ either version 2.1 of the License, or (at your option) any   
+later version.                                               
+                                                              
+ This source is distributed in the hope that it will be       
+ useful, but WITHOUT ANY WARRANTY; without even the implied   
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+ PURPOSE.  See the GNU Lesser General Public License for more 
+ details.                                                     
+                                                              
+ You should have received a copy of the GNU Lesser General    
+ Public License along with this source; if not, download it   
+ from http://www.opencores.org/lgpl.shtml                     
+                                                              
+*******************************************************************/
+
+
+`timescale 1ns/1ps
+module sdrc_top 
+           (
+                   cfg_sdr_width       ,
+                   cfg_colbits         ,
+                    
+                // Input to sdram ctrl
+                    app_req        ,                   
+                    app_req_addr   ,
+                    app_req_len    ,
+                    app_req_wr_n   ,
+                    app_req_wrap   ,
+                    app_req_ack    ,                  
+//                  app_busy_n     ,                   
+                    app_wr_en_n    ,                   
+                    app_wr_next_req,                   
+                    app_rd_valid   ,                   
+                    app_last_rd    ,                    
+                    app_last_wr,
+                    app_wr_data    ,
+                    app_rd_data    ,
+                    delay_config_reg2,
+
+               /* Interface to SDRAMs */
+                    sdram_clk           ,
+                    sdram_resetn        ,
+                    sdr_cs_n            ,
+                    sdr_cke             ,
+                    sdr_ras_n           ,
+                    sdr_cas_n           ,
+                    sdr_we_n            ,
+                    sdr_dqm             ,
+                    sdr_ba              ,
+                    sdr_addr            , 
+                    pad_sdr_din         , // SDRA Data Input
+                    sdr_dout            , // SDRAM Data Output
+                    sdr_den_n           , // SDRAM Data Output enable
+                    
+               /* Parameters */
+                    sdr_init_done       ,
+                    cfg_req_depth       ,              //how many req. buffer should hold
+                    cfg_sdr_en          ,
+                    cfg_sdr_mode_reg    ,
+                    cfg_sdr_tras_d      ,
+                    cfg_sdr_trp_d       ,
+                    cfg_sdr_trcd_d      ,
+                    cfg_sdr_cas         ,
+                    cfg_sdr_trcar_d     ,
+                    cfg_sdr_twr_d       ,
+                    cfg_sdr_rfsh        ,
+                   cfg_sdr_rfmax
+           );
+  
+  `define SDR_REQ_ID_W       4
+
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W   3
+
+// B2X Command
+
+`define OP_PRE           2'b00
+`define OP_ACT           2'b01
+`define OP_RD            2'b10
+`define OP_WR            2'b11
+
+// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
+
+`define SDR_DESEL        4'b1111
+`define SDR_NOOP         4'b0111
+`define SDR_ACTIVATE     4'b0011
+`define SDR_READ         4'b0101
+`define SDR_WRITE        4'b0100
+`define SDR_BT           4'b0110
+`define SDR_PRECHARGE    4'b0010
+`define SDR_REFRESH      4'b0001
+`define SDR_MODE         4'b0000
+
+`define  ASIC            1'b1
+`define  FPGA            1'b0
+`define  TARGET_DESIGN   `ASIC
+// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
+`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
+
+parameter      APP_AW   = 26;  // Application Address Width
+parameter      APP_DW   = 64;  // Application Data Width 
+parameter      APP_BW   = 8;   // Application Byte Width
+parameter      APP_RW   = 9;   // Application Request Width
+
+parameter      SDR_DW   = 64;  // SDR Data Width 
+parameter      SDR_BW   = 8;   // SDR Byte Width
+             
+parameter      dw       = 64;  // data width
+parameter      tw       = 8;   // tag id width
+parameter      bl       = 9;   // burst_lenght_width 
+
+//-----------------------------------------------
+// Global Variable
+// ----------------------------------------------
+input                   sdram_clk          ; // SDRAM Clock 
+input                   sdram_resetn       ; // Reset Signal
+input [1:0]             cfg_sdr_width      ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
+input [1:0]             cfg_colbits        ; // 2'b00 - 8 Bit column address, 
+                                             // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits
+
+//--------------------------------------
+// Wish Bone Interface
+// -------------------------------------      
+//input                   wb_rst_i           ;
+//input                   wb_clk_i           ;
+//
+//input                   wb_stb_i           ;
+//output                  wb_ack_o           ;
+//input [APP_AW-1:0]            wb_addr_i          ;
+//input                   wb_we_i            ; // 1 - Write, 0 - Read
+//input [dw-1:0]          wb_dat_i           ;
+//input [dw/8-1:0]        wb_sel_i           ; // Byte enable
+//output [dw-1:0]         wb_dat_o           ;
+//input                   wb_cyc_i           ;
+//input  [2:0]            wb_cti_i           ;
+
+//------------------------------------------------
+// Interface to SDRAMs
+//------------------------------------------------
+output                  sdr_cke             ; // SDRAM CKE
+output                                 sdr_cs_n            ; // SDRAM Chip Select
+output                  sdr_ras_n           ; // SDRAM ras
+output                  sdr_cas_n           ; // SDRAM cas
+output                         sdr_we_n            ; // SDRAM write enable
+output [SDR_BW-1:0]    sdr_dqm             ; // SDRAM Data Mask
+output [1:0]               sdr_ba              ; // SDRAM Bank Enable
+output [12:0]              sdr_addr            ; // SDRAM Address
+input [SDR_DW-1:0]         pad_sdr_din         ; // SDRA Data Input
+output [SDR_DW-1:0]    sdr_dout            ; // SDRAM Data Output
+output [SDR_BW-1:0]    sdr_den_n           ; // SDRAM Data Output enable
+//------------------------------------------------
+// Configuration Parameter // vis: changed input and output pins to wire
+//------------------------------------------------
+
+output                           sdr_init_done       ; // Indicate SDRAM Initialisation Done
+input [3:0]                     cfg_sdr_tras_d      ; // Active to precharge delay
+input [3:0]                      cfg_sdr_trp_d       ; // Precharge to active delay
+input [3:0]                      cfg_sdr_trcd_d      ; // Active to R/W delay
+input                                   cfg_sdr_en          ; // Enable SDRAM controller
+input [1:0]                         cfg_req_depth       ; // Maximum Request accepted by SDRAM controller
+input [12:0]                            cfg_sdr_mode_reg    ;
+input [2:0]                             cfg_sdr_cas         ; // SDRAM CAS Latency
+input [3:0]                                 cfg_sdr_trcar_d     ; // Auto-refresh period
+input [3:0]                      cfg_sdr_twr_d       ; // Write recovery delay
+input [`SDR_RFSH_TIMER_W-1 : 0]  cfg_sdr_rfsh;
+input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax;
+
+
+/*
+assign cfg_req_depth  = 2'h3;          //how many req. buffer should hold
+assign cfg_sdr_en = 1'b1;
+assign cfg_sdr_mode_reg = 13'h033;
+assign cfg_sdr_tras_d = 4'h4;
+assign cfg_sdr_trp_d = 4'h2;
+assign cfg_sdr_trcd_d = 4'h2;
+assign cfg_sdr_cas = 3'h3;
+assign cfg_sdr_trcar_d = 4'h7;
+assign cfg_sdr_twr_d = 4'h1;
+assign cfg_sdr_rfsh = 12'h100; // reduced from 12'hC35
+assign cfg_sdr_rfmax = 3'h6;*/
+//assign cfg_colbits = 2'b00;
+//assign cfg_sdr_width = 2'b00;
+
+//--------------------------------------------
+// SDRAM controller Interface 
+//--------------------------------------------
+input                  app_req            ; // SDRAM request
+input                  app_req_wrap       ; // SDRAM wrap 
+input [APP_AW-1:0]     app_req_addr       ; // SDRAM Request Address
+input [bl-1:0]         app_req_len        ;
+input                  app_req_wr_n       ; // 0 - Write, 1 -> Read
+output                 app_req_ack        ; // SDRAM request Accepted
+wire                   app_busy_n         ; // 0 -> sdr busy
+input [dw/8-1:0]       app_wr_en_n        ; // Active low sdr byte-wise write data valid
+output                 app_wr_next_req    ; // Ready to accept the next write
+output                 app_rd_valid       ; // sdr read valid
+output                 app_last_rd        ; // Indicate last Read of Burst Transfer
+output                 app_last_wr        ; // Indicate last Write of Burst Transfer
+input [dw-1:0]         app_wr_data        ; // sdr write data
+output  [dw-1:0]       app_rd_data        ; // sdr read data
+
+input [3:0] delay_config_reg2;
+
+/****************************************
+*  These logic has to be implemented using Pads
+*  **************************************/
+/*wire  [SDR_DW-1:0]    pad_sdr_din         ; // SDRA Data Input
+wire  [SDR_DW-1:0]    sdr_dout            ; // SDRAM Data Output
+wire  [SDR_BW-1:0]    sdr_den_n           ; // SDRAM Data Output enable
+wire [SDR_DW-1:0]        sdr_dq              ; // SDRA Data Input/output*/
+
+/*assign sdr_dq0 = sdr_dq[31:0];
+assign sdr_dq1 = sdr_dq[63:32];
+
+
+assign   sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout :  {SDR_DW{1'bz}}; 
+assign   pad_sdr_din = {sdr_dq1, sdr_dq0};*/
+
+
+
+// sdram pad clock is routed back through pad
+// SDRAM Clock from Pad, used for registering Read Data
+wire sdram_pad_clk;
+parallel_prog_delay_cell delay_inst_for_sdram_clk_pad(.in_clk(sdram_clk), .delay_config_reg(delay_config_reg2), .delayed_clk(sdram_pad_clk));
+
+
+
+sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
+          .clk                (sdram_clk          ) ,
+          .pad_clk            (sdram_pad_clk      ) ,
+          .reset_n            (sdram_resetn       ) ,
+          .sdr_width          (cfg_sdr_width      ) ,
+          .cfg_colbits        (cfg_colbits        ) ,
+
+               /* Request from app */
+          .app_req            (app_req            ) ,// Transfer Request
+          .app_req_addr       (app_req_addr       ) ,// SDRAM Address
+          .app_req_len        (app_req_len        ) ,// Burst Length (in 16 bit words)
+          .app_req_wrap       (app_req_wrap       ) ,// Wrap mode request 
+          .app_req_wr_n              (app_req_wr_n       ) ,// 0 => Write request, 1 => read req
+          .app_req_ack        (app_req_ack        ) ,// Request has been accepted
+          .cfg_req_depth      (cfg_req_depth      ) ,//how many req. buffer should hold
+               
+          .app_wr_data        (app_wr_data        ) ,
+          .app_wr_en_n        (app_wr_en_n        ) ,
+          .app_rd_data        (app_rd_data        ) ,
+          .app_rd_valid       (app_rd_valid       ) ,
+                 .app_last_rd        (app_last_rd        ) ,
+          .app_last_wr        (app_last_wr        ) ,
+          .app_wr_next_req    (app_wr_next_req    ) ,
+          .sdr_init_done      (sdr_init_done      ) ,
+          .app_req_dma_last   (app_req            ) ,
+               /* Interface to SDRAMs */
+          .sdr_cs_n           (sdr_cs_n           ) ,
+          .sdr_cke            (sdr_cke            ) ,
+          .sdr_ras_n          (sdr_ras_n          ) ,
+          .sdr_cas_n          (sdr_cas_n          ) ,
+          .sdr_we_n           (sdr_we_n           ) ,
+          .sdr_dqm            (sdr_dqm            ) ,
+          .sdr_ba             (sdr_ba             ) ,
+          .sdr_addr           (sdr_addr           ) , 
+          .pad_sdr_din        (pad_sdr_din        ) ,
+          .sdr_dout           (sdr_dout           ) ,
+          .sdr_den_n          (sdr_den_n          ) ,
+               /* Parameters */
+          .cfg_sdr_en         (cfg_sdr_en         ) ,
+          .cfg_sdr_mode_reg   (cfg_sdr_mode_reg   ) ,
+          .cfg_sdr_tras_d     (cfg_sdr_tras_d     ) ,
+          .cfg_sdr_trp_d      (cfg_sdr_trp_d      ) ,
+          .cfg_sdr_trcd_d     (cfg_sdr_trcd_d     ) ,
+          .cfg_sdr_cas        (cfg_sdr_cas        ) ,
+          .cfg_sdr_trcar_d    (cfg_sdr_trcar_d    ) ,
+          .cfg_sdr_twr_d      (cfg_sdr_twr_d      ) ,
+          .cfg_sdr_rfsh       (cfg_sdr_rfsh       ) ,
+          .cfg_sdr_rfmax      (cfg_sdr_rfmax      ) 
+              );
+   
+endmodule // sdrc_core
diff --git a/src/peripherals/sdram/controller/sdrc_xfr_ctl.v b/src/peripherals/sdram/controller/sdrc_xfr_ctl.v
new file mode 100755 (executable)
index 0000000..8acd980
--- /dev/null
@@ -0,0 +1,939 @@
+/*********************************************************************
+                                                              
+  SDRAM Controller Transfer control
+                                                              
+  This file is part of the sdram controller project           
+  http://www.opencores.org/cores/sdr_ctrl/                    
+                                                              
+  Description: SDRAM Controller Transfer control
+
+  This module takes requests from sdrc_bank_ctl and runs the
+  transfer. The input request is guaranteed to be in a bank that is
+  precharged and activated. This block runs the transfer until a
+  burst boundary is reached, then issues another read/write command
+  to sequentially step thru memory if wrap=0, until the transfer is
+  completed.
+   
+  if a read transfer finishes and the caddr is not at a burst boundary 
+  a burst terminate command is issued unless another read/write or
+  precharge to the same bank is pending.
+  
+  if a write transfer finishes and the caddr is not at a burst boundary 
+  a burst terminate command is issued unless a read/write is pending.
+  
+   If a refresh request is made, the bank_ctl will be held off until
+   the number of refreshes requested are completed.
+
+   This block also handles SDRAM initialization.
+  
+
+  To Do:                                                      
+    nothing                                                   
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesha@opencores.org                 
+  Version  : 1.0 - 8th Jan 2012
+                                                              
+
+                                                             
+ Copyright (C) 2000 Authors and OPENCORES.ORG                
+                                                             
+ This source file may be used and distributed without         
+ restriction provided that this copyright statement is not    
+ removed from the file and that any derivative work contains  
+ the original copyright notice and the associated disclaimer. 
+                                                              
+ This source file is free software; you can redistribute it   
+ and/or modify it under the terms of the GNU Lesser General   
+ Public License as published by the Free Software Foundation; 
+ either version 2.1 of the License, or (at your option) any   
+later version.                                               
+                                                              
+ This source is distributed in the hope that it will be       
+ useful, but WITHOUT ANY WARRANTY; without even the implied   
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+ PURPOSE.  See the GNU Lesser General Public License for more 
+ details.                                                     
+                                                              
+ You should have received a copy of the GNU Lesser General    
+ Public License along with this source; if not, download it   
+ from http://www.opencores.org/lgpl.shtml                     
+                                                              
+*******************************************************************/
+
+
+
+module sdrc_xfr_ctl (clk,
+                   reset_n,
+                   
+                   /* Transfer request from bank_ctl */
+                   r2x_idle,      // Req is idle
+                   b2x_idle,      // All banks are idle
+                   b2x_req,       // Req from bank_ctl
+                   b2x_start,     // first chunk of transfer
+                   b2x_last,      // last chunk of transfer
+                   b2x_id,        // Transfer ID
+                   b2x_ba,        // bank address
+                   b2x_addr,      // row/col address
+                   b2x_len,       // transfer length
+                   b2x_cmd,       // transfer command
+                   b2x_wrap,      // Wrap mode transfer
+                   x2b_ack,       // command accepted
+                    
+                   /* Status to bank_ctl, req_gen */
+                   b2x_tras_ok,   // Tras for all banks expired
+                   x2b_refresh,   // We did a refresh
+                   x2b_pre_ok,    // OK to do a precharge (per bank)
+                   x2b_act_ok,    // OK to do an activate
+                   x2b_rdok,      // OK to do a read
+                   x2b_wrok,      // OK to do a write
+                   
+                   /* SDRAM I/O */
+                   sdr_cs_n,
+                   sdr_cke,
+                   sdr_ras_n,
+                   sdr_cas_n,
+                   sdr_we_n,
+                   sdr_dqm,
+                   sdr_ba,
+                   sdr_addr, 
+                   sdr_din,
+                   sdr_dout,
+                   sdr_den_n,
+                   
+                   /* Data Flow to the app */
+                   x2a_rdstart,
+                   x2a_wrstart,
+                   x2a_rdlast,
+                   x2a_wrlast,
+                   x2a_id,
+                   a2x_wrdt,
+                   a2x_wren_n,
+                   x2a_wrnext,
+                   x2a_rddt,
+                   x2a_rdok,
+                   sdr_init_done,
+                   
+                   /* SDRAM Parameters */
+                   sdram_enable,
+                   sdram_mode_reg,
+                   
+                   /* output for generate row address of the transfer */
+                   xfr_bank_sel,
+
+                   /* SDRAM Timing */
+                   cas_latency,
+                   trp_delay,     // Precharge to refresh delay
+                   trcar_delay,   // Auto-refresh period
+                   twr_delay,     // Write recovery delay
+                   rfsh_time,     // time per row (31.25 or 15.6125 uS)
+                   rfsh_rmax);    // Number of rows to rfsh at a time (<120uS)
+   
+
+`define SDR_REQ_ID_W       4
+
+`define SDR_RFSH_TIMER_W    12
+`define SDR_RFSH_ROW_CNT_W   3
+
+// B2X Command
+
+`define OP_PRE           2'b00
+`define OP_ACT           2'b01
+`define OP_RD            2'b10
+`define OP_WR            2'b11
+
+// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
+
+`define SDR_DESEL        4'b1111
+`define SDR_NOOP         4'b0111
+`define SDR_ACTIVATE     4'b0011
+`define SDR_READ         4'b0101
+`define SDR_WRITE        4'b0100
+`define SDR_BT           4'b0110
+`define SDR_PRECHARGE    4'b0010
+`define SDR_REFRESH      4'b0001
+`define SDR_MODE         4'b0000
+
+`define  ASIC            1'b1
+`define  FPGA            1'b0
+`define  TARGET_DESIGN   `ASIC
+// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
+`define  REQ_BW    (`TARGET_DESIGN == `FPGA) ? 6 : 12   //  Request Width
+
+parameter  SDR_DW   = 64;  // SDR Data Width 
+parameter  SDR_BW   = 8;   // SDR Byte Width
+
+
+input            clk, reset_n; 
+
+   /* Req from bank_ctl */
+input                  b2x_req, b2x_start, b2x_last, b2x_tras_ok,
+                               b2x_wrap, r2x_idle, b2x_idle; 
+input [`SDR_REQ_ID_W-1:0]      b2x_id;
+input [1:0]                    b2x_ba;
+input [12:0]           b2x_addr;
+input [`REQ_BW-1:0]    b2x_len;
+input [1:0]                    b2x_cmd;
+output                         x2b_ack;
+
+/* Status to bank_ctl */
+output [3:0]           x2b_pre_ok;
+output                         x2b_refresh, x2b_act_ok, x2b_rdok,
+                               x2b_wrok;
+/* Data Flow to the app */
+output                         x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast;
+output [`SDR_REQ_ID_W-1:0]     x2a_id;
+
+input [SDR_DW-1:0]     a2x_wrdt;
+input [SDR_BW-1:0]     a2x_wren_n;
+output [SDR_DW-1:0]    x2a_rddt;
+output                         x2a_wrnext, x2a_rdok, sdr_init_done;
+               
+/* Interface to SDRAMs */
+output                         sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n,
+                               sdr_we_n; 
+output [SDR_BW-1:0]    sdr_dqm;
+output [1:0]           sdr_ba;
+output [12:0]          sdr_addr;
+input [SDR_DW-1:0]     sdr_din;
+output [SDR_DW-1:0]    sdr_dout;
+output [SDR_BW-1:0]    sdr_den_n;
+
+   output [1:0]                        xfr_bank_sel;
+
+   input                       sdram_enable;
+   input [12:0]                sdram_mode_reg;
+   input [2:0]                         cas_latency;
+   input [3:0]                         trp_delay, trcar_delay, twr_delay;
+   input [`SDR_RFSH_TIMER_W-1 : 0] rfsh_time;
+   input [`SDR_RFSH_ROW_CNT_W-1:0] rfsh_rmax;
+   
+// vish change mode reg ext
+   //reg [12:0]           sdram_mode_ext_reg;
+   reg init_delay_done; // winbond initial delay done flag : vish change
+   reg mode_set;
+   reg wr_mode_set;
+
+   /************************************************************************/
+   // Internal Nets
+
+   `define XFR_IDLE        2'b00
+   `define XFR_WRITE       2'b01
+   `define XFR_READ        2'b10
+   `define XFR_RDWT        2'b11
+
+   reg [1:0]                   xfr_st, next_xfr_st;
+   reg [12:0]                  xfr_caddr;
+   wire                        last_burst;
+   wire                        x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast;
+   reg                                 l_start, l_last, l_wrap;
+   wire [`SDR_REQ_ID_W-1:0]    x2a_id;
+   reg [`SDR_REQ_ID_W-1:0]     l_id;
+   wire [1:0]                  xfr_ba;
+   reg [1:0]                   l_ba;
+   wire [12:0]                         xfr_addr;
+   wire [`REQ_BW-1:0]  xfr_len, next_xfr_len;
+   reg [`REQ_BW-1:0]   l_len;
+
+   reg                                 mgmt_idle, mgmt_req;
+   reg [3:0]                   mgmt_cmd;
+   reg [12:0]                  mgmt_addr;
+   reg [1:0]                   mgmt_ba;
+
+   reg                                 sel_mgmt, sel_b2x;
+   reg                                 cb_pre_ok, rdok, wrok, wr_next,
+                               rd_next, sdr_init_done, act_cmd, d_act_cmd;
+   wire [3:0]                  b2x_sdr_cmd, xfr_cmd;
+   reg [3:0]                   i_xfr_cmd;
+   wire                        mgmt_ack, x2b_ack, b2x_read, b2x_write, 
+                               b2x_prechg, d_rd_next, dt_next, xfr_end,
+                               rd_pipe_mt, ld_xfr, rd_last, d_rd_last, 
+                               wr_last, l_xfr_end, rd_start, d_rd_start,
+                               wr_start, page_hit, burst_bdry, xfr_wrap,
+                               b2x_prechg_hit;
+   reg [6:0]                   l_rd_next, l_rd_start, l_rd_last;
+
+//vish change
+   reg[11:0]  rg_initial_delay;
+
+   
+   assign b2x_read = (b2x_cmd == `OP_RD) ? 1'b1 : 1'b0;
+
+   assign b2x_write = (b2x_cmd == `OP_WR) ? 1'b1 : 1'b0;
+
+   assign b2x_prechg = (b2x_cmd == `OP_PRE) ? 1'b1 : 1'b0;
+   
+   assign b2x_sdr_cmd = (b2x_cmd == `OP_PRE) ? `SDR_PRECHARGE :
+                       (b2x_cmd == `OP_ACT) ? `SDR_ACTIVATE :
+                       (b2x_cmd == `OP_RD) ? `SDR_READ :
+                       (b2x_cmd == `OP_WR) ? `SDR_WRITE : `SDR_DESEL;
+
+   assign page_hit = (b2x_ba == l_ba) ? 1'b1 : 1'b0;
+
+   assign b2x_prechg_hit = b2x_prechg & page_hit;
+   
+   assign xfr_cmd = (sel_mgmt) ? mgmt_cmd :
+                   (sel_b2x) ? b2x_sdr_cmd : i_xfr_cmd;
+
+   assign xfr_addr = (sel_mgmt) ? mgmt_addr : 
+                    (sel_b2x) ? b2x_addr : xfr_caddr+1;
+
+   assign mgmt_ack = sel_mgmt;
+
+   assign x2b_ack = sel_b2x;
+
+   assign ld_xfr = sel_b2x & (b2x_read | b2x_write);
+   
+   assign xfr_len = (ld_xfr) ? b2x_len : l_len;
+
+   //assign next_xfr_len = (l_xfr_end && !ld_xfr) ? l_len : xfr_len - 1;
+   assign next_xfr_len = (ld_xfr) ? b2x_len : 
+                        (l_xfr_end) ? l_len:  l_len - 1;
+
+   assign d_rd_next = (cas_latency == 3'b001) ? l_rd_next[2] :
+                     (cas_latency == 3'b010) ? l_rd_next[3] :
+                     (cas_latency == 3'b011) ? l_rd_next[4] :
+                     (cas_latency == 3'b100) ? l_rd_next[5] :
+                     l_rd_next[6];
+
+   assign d_rd_last = (cas_latency == 3'b001) ? l_rd_last[2] :
+                     (cas_latency == 3'b010) ? l_rd_last[3] :
+                     (cas_latency == 3'b011) ? l_rd_last[4] :
+                     (cas_latency == 3'b100) ? l_rd_last[5] :
+                     l_rd_last[6];
+
+   assign d_rd_start = (cas_latency == 3'b001) ? l_rd_start[2] :
+                      (cas_latency == 3'b010) ? l_rd_start[3] :
+                      (cas_latency == 3'b011) ? l_rd_start[4] :
+                      (cas_latency == 3'b100) ? l_rd_start[5] :
+                      l_rd_start[6];
+
+   assign rd_pipe_mt = (cas_latency == 3'b001) ? ~|l_rd_next[1:0] :
+                      (cas_latency == 3'b010) ? ~|l_rd_next[2:0] :
+                      (cas_latency == 3'b011) ? ~|l_rd_next[3:0] :
+                      (cas_latency == 3'b100) ? ~|l_rd_next[4:0] :
+                      ~|l_rd_next[5:0];
+
+   assign dt_next = wr_next | d_rd_next;
+
+   assign xfr_end = ~|xfr_len;
+
+   assign l_xfr_end = ~|(l_len-1);
+
+   assign rd_start = ld_xfr & b2x_read & b2x_start;
+
+   assign wr_start = ld_xfr & b2x_write & b2x_start;
+   
+   assign rd_last = rd_next & last_burst & ~|xfr_len[`REQ_BW-1:1];
+
+   //assign wr_last = wr_next & last_burst & ~|xfr_len[APP_RW-1:1];
+
+   assign wr_last = last_burst & ~|xfr_len[`REQ_BW-1:1];
+   
+   //assign xfr_ba = (ld_xfr) ? b2x_ba : l_ba;
+   assign xfr_ba = (sel_mgmt) ? mgmt_ba : 
+                  (sel_b2x) ? b2x_ba : l_ba;
+
+   assign xfr_wrap = (ld_xfr) ? b2x_wrap : l_wrap;
+   
+//   assign burst_bdry = ~|xfr_caddr[2:0];
+   wire [1:0] xfr_caddr_lsb = (xfr_caddr[1:0]+1);
+   assign burst_bdry = ~|(xfr_caddr_lsb[1:0]);
+  
+   always @ (posedge clk) begin
+      if (~reset_n) begin
+        xfr_caddr <= 13'b0;
+        l_start <= 1'b0;
+        l_last <= 1'b0;
+        l_wrap <= 1'b0;
+        l_id <= 0;
+        l_ba <= 0;
+        l_len <= 0;
+        l_rd_next <= 7'b0;
+        l_rd_start <= 7'b0;
+        l_rd_last <= 7'b0;
+        act_cmd <= 1'b0;
+        d_act_cmd <= 1'b0;
+        xfr_st <= `XFR_IDLE;
+      end // if (~reset_n)
+
+      else begin
+        xfr_caddr <= (ld_xfr) ? b2x_addr :
+                     (rd_next | wr_next) ? xfr_caddr + 1 : xfr_caddr; 
+        l_start <= (dt_next) ? 1'b0 : 
+                  (ld_xfr) ? b2x_start : l_start;
+        l_last <= (ld_xfr) ? b2x_last : l_last;
+        l_wrap <= (ld_xfr) ? b2x_wrap : l_wrap;
+        l_id <= (ld_xfr) ? b2x_id : l_id;
+        l_ba <= (ld_xfr) ? b2x_ba : l_ba;
+        l_len <= next_xfr_len;
+        l_rd_next <= {l_rd_next[5:0], rd_next};
+        l_rd_start <= {l_rd_start[5:0], rd_start};
+        l_rd_last <= {l_rd_last[5:0], rd_last};
+        act_cmd <= (xfr_cmd == `SDR_ACTIVATE) ? 1'b1 : 1'b0;
+        d_act_cmd <= act_cmd;
+        xfr_st <= next_xfr_st;
+      end // else: !if(~reset_n)
+      
+   end // always @ (posedge clk)
+   
+
+   always @ (*) begin 
+      case (xfr_st)
+
+       `XFR_IDLE : begin
+
+          sel_mgmt = mgmt_req;
+          sel_b2x = ~mgmt_req & sdr_init_done & b2x_req;
+          i_xfr_cmd = `SDR_DESEL;
+          rd_next = ~mgmt_req & sdr_init_done & b2x_req & b2x_read;
+          wr_next = ~mgmt_req & sdr_init_done & b2x_req & b2x_write;
+          rdok = ~mgmt_req;
+          cb_pre_ok = 1'b1;
+          wrok = ~mgmt_req;
+          next_xfr_st = (mgmt_req | ~sdr_init_done) ? `XFR_IDLE :
+                        (~b2x_req) ? `XFR_IDLE :
+                        (b2x_read) ? `XFR_READ :
+                        (b2x_write) ? `XFR_WRITE : `XFR_IDLE;
+
+       end // case: `XFR_IDLE
+          
+       `XFR_READ : begin
+          rd_next = ~l_xfr_end |
+                    l_xfr_end & ~mgmt_req & b2x_req & b2x_read;
+          wr_next = 1'b0;
+          rdok = l_xfr_end & ~mgmt_req;
+          // Break the timing path for FPGA Based Design
+          cb_pre_ok = (`TARGET_DESIGN == `FPGA) ? 1'b0 : l_xfr_end;
+          wrok = 1'b0;
+          sel_mgmt = 1'b0;
+
+          if (l_xfr_end) begin           // end of transfer
+
+             if (~l_wrap) begin
+                // Current transfer was not wrap mode, may need BT
+                // If next cmd is a R or W or PRE to same bank allow
+                // it else issue BT 
+                // This is a little pessimistic since BT is issued
+                // for non-wrap mode transfers even if the transfer
+                // ends on a burst boundary, but is felt to be of
+                // minimal performance impact.
+
+                i_xfr_cmd = `SDR_BT;
+                sel_b2x = b2x_req & ~mgmt_req & (b2x_read | b2x_prechg_hit);
+
+             end // if (~l_wrap)
+             
+             else begin
+                // Wrap mode transfer, by definition is end of burst
+                // boundary 
+
+                i_xfr_cmd = `SDR_DESEL;
+                sel_b2x = b2x_req & ~mgmt_req & ~b2x_write;
+
+             end // else: !if(~l_wrap)
+                
+             next_xfr_st = (sdr_init_done) ? ((b2x_req & ~mgmt_req & b2x_read) ? `XFR_READ : `XFR_RDWT) : `XFR_IDLE;
+
+          end // if (l_xfr_end)
+
+          else begin
+             // Not end of transfer
+             // If current transfer was not wrap mode and we are at
+             // the start of a burst boundary issue another R cmd to
+             // step sequemtially thru memory, ELSE,
+             // issue precharge/activate commands from the bank control
+
+             i_xfr_cmd = (burst_bdry & ~l_wrap) ? `SDR_READ : `SDR_DESEL;
+             sel_b2x = ~(burst_bdry & ~l_wrap) & b2x_req;
+             next_xfr_st = `XFR_READ;
+
+          end // else: !if(l_xfr_end)
+          
+       end // case: `XFR_READ
+       
+       `XFR_RDWT : begin 
+          rd_next = ~mgmt_req & b2x_req & b2x_read;
+          wr_next = rd_pipe_mt & ~mgmt_req & b2x_req & b2x_write;
+          rdok = ~mgmt_req;
+          cb_pre_ok = 1'b1;
+          wrok = rd_pipe_mt & ~mgmt_req;
+
+          sel_mgmt = mgmt_req;
+          
+          sel_b2x = ~mgmt_req & b2x_req;
+
+          i_xfr_cmd = `SDR_DESEL;
+
+          next_xfr_st = (~mgmt_req & b2x_req & b2x_read) ? `XFR_READ : 
+                        (~rd_pipe_mt) ? `XFR_RDWT :
+                        (~mgmt_req & b2x_req & b2x_write) ? `XFR_WRITE : 
+                        `XFR_IDLE;
+
+       end // case: `XFR_RDWT
+       
+       `XFR_WRITE : begin
+          rd_next = l_xfr_end & ~mgmt_req & b2x_req & b2x_read;
+          wr_next = ~l_xfr_end |
+                    l_xfr_end & ~mgmt_req & b2x_req & b2x_write;
+          rdok = l_xfr_end & ~mgmt_req;
+          cb_pre_ok = 1'b0;
+          wrok = l_xfr_end & ~mgmt_req;
+          sel_mgmt = 1'b0;
+
+          if (l_xfr_end) begin           // End of transfer
+
+             if (~l_wrap) begin
+                //&nb