src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11
  12 from nmutil.iocontrol import RecordObject
  13 from nmutil.extend import exts
  14
  15 from soc.decoder.power_regspec_map import regspec_decode_read
  16 from soc.decoder.power_regspec_map import regspec_decode_write
  17 from soc.decoder.power_decoder import create_pdecode
  18 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
  19                                      CRInSel, CROutSel,
  20                                      LdstLen, In1Sel, In2Sel, In3Sel,
  21                                      OutSel, SPR, RC, LDSTMode)
  22 from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
  23 from soc.consts import MSR
  24
  25 from soc.regfile.regfiles import FastRegs
  26 from soc.consts import TT
  27 from soc.config.state import CoreState
  28
  29
  30 def decode_spr_num(spr):
  31     return Cat(spr[5:10], spr[0:5])
  32
  33
  34 def instr_is_priv(m, op, insn):
  35     """determines if the instruction is privileged or not
  36     """
  37     comb = m.d.comb
  38     is_priv_insn = Signal(reset_less=True)
  39     with m.Switch(op):
  40         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  41                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  42             comb += is_priv_insn.eq(1)
  43         # XXX TODO
  44         #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  45         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  46             with m.If(insn[20]):  # field XFX.spr[-1] i think
  47                 comb += is_priv_insn.eq(1)
  48     return is_priv_insn
  49
  50
  51 class SPRMap(Elaboratable):
  52     """SPRMap: maps POWER9 SPR numbers to internal enum values
  53     """
  54
  55     def __init__(self):
  56         self.spr_i = Signal(10, reset_less=True)
  57         self.spr_o = Signal(SPR, reset_less=True)
  58
  59     def elaborate(self, platform):
  60         m = Module()
  61         with m.Switch(self.spr_i):
  62             for i, x in enumerate(SPR):
  63                 with m.Case(x.value):
  64                     m.d.comb += self.spr_o.eq(i)
  65         return m
  66
  67
  68 class DecodeA(Elaboratable):
  69     """DecodeA from instruction
  70
  71     decodes register RA, whether immediate-zero, implicit and
  72     explicit CSRs
  73     """
  74
  75     def __init__(self, dec):
  76         self.dec = dec
  77         self.sel_in = Signal(In1Sel, reset_less=True)
  78         self.insn_in = Signal(32, reset_less=True)
  79         self.reg_out = Data(5, name="reg_a")
  80         self.immz_out = Signal(reset_less=True)
  81         self.spr_out = Data(SPR, "spr_a")
  82         self.fast_out = Data(3, "fast_a")
  83
  84     def elaborate(self, platform):
  85         m = Module()
  86         comb = m.d.comb
  87         m.submodules.sprmap = sprmap = SPRMap()
  88
  89         # select Register A field
  90         ra = Signal(5, reset_less=True)
  91         comb += ra.eq(self.dec.RA)
  92         with m.If((self.sel_in == In1Sel.RA) |
  93                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  94                    (ra != Const(0, 5)))):
  95             comb += self.reg_out.data.eq(ra)
  96             comb += self.reg_out.ok.eq(1)
  97
  98         # zero immediate requested
  99         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 100                   (self.reg_out.data == Const(0, 5))):
 101             comb += self.immz_out.eq(1)
 102
 103         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 104         with m.If(self.sel_in == In1Sel.RS):
 105             comb += self.reg_out.data.eq(self.dec.RS)
 106             comb += self.reg_out.ok.eq(1)
 107
 108         # decode Fast-SPR based on instruction type
 109         op = self.dec.op
 110         with m.Switch(op.internal_op):
 111
 112             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 113             with m.Case(MicrOp.OP_BC):
 114                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 115                     # constant: CTR
 116                     comb += self.fast_out.data.eq(FastRegs.CTR)
 117                     comb += self.fast_out.ok.eq(1)
 118             with m.Case(MicrOp.OP_BCREG):
 119                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 120                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 121                 with m.If(xo9 & ~xo5):
 122                     # constant: CTR
 123                     comb += self.fast_out.data.eq(FastRegs.CTR)
 124                     comb += self.fast_out.ok.eq(1)
 125
 126             # MFSPR move from SPRs
 127             with m.Case(MicrOp.OP_MFSPR):
 128                 spr = Signal(10, reset_less=True)
 129                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 130                 with m.Switch(spr):
 131                     # fast SPRs
 132                     with m.Case(SPR.CTR.value):
 133                         comb += self.fast_out.data.eq(FastRegs.CTR)
 134                         comb += self.fast_out.ok.eq(1)
 135                     with m.Case(SPR.LR.value):
 136                         comb += self.fast_out.data.eq(FastRegs.LR)
 137                         comb += self.fast_out.ok.eq(1)
 138                     with m.Case(SPR.TAR.value):
 139                         comb += self.fast_out.data.eq(FastRegs.TAR)
 140                         comb += self.fast_out.ok.eq(1)
 141                     with m.Case(SPR.SRR0.value):
 142                         comb += self.fast_out.data.eq(FastRegs.SRR0)
 143                         comb += self.fast_out.ok.eq(1)
 144                     with m.Case(SPR.SRR1.value):
 145                         comb += self.fast_out.data.eq(FastRegs.SRR1)
 146                         comb += self.fast_out.ok.eq(1)
 147                     with m.Case(SPR.XER.value):
 148                         pass  # do nothing
 149                     # : map to internal SPR numbers
 150                     # XXX TODO: dec and tb not to go through mapping.
 151                     with m.Default():
 152                         comb += sprmap.spr_i.eq(spr)
 153                         comb += self.spr_out.data.eq(sprmap.spr_o)
 154                         comb += self.spr_out.ok.eq(1)
 155
 156         return m
 157
 158
 159 class DecodeB(Elaboratable):
 160     """DecodeB from instruction
 161
 162     decodes register RB, different forms of immediate (signed, unsigned),
 163     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 164     by industry-standard convention, "lane 2" is where fully-decoded
 165     immediates are muxed in.
 166     """
 167
 168     def __init__(self, dec):
 169         self.dec = dec
 170         self.sel_in = Signal(In2Sel, reset_less=True)
 171         self.insn_in = Signal(32, reset_less=True)
 172         self.reg_out = Data(5, "reg_b")
 173         self.imm_out = Data(64, "imm_b")
 174         self.fast_out = Data(3, "fast_b")
 175
 176     def elaborate(self, platform):
 177         m = Module()
 178         comb = m.d.comb
 179
 180         # select Register B field
 181         with m.Switch(self.sel_in):
 182             with m.Case(In2Sel.RB):
 183                 comb += self.reg_out.data.eq(self.dec.RB)
 184                 comb += self.reg_out.ok.eq(1)
 185             with m.Case(In2Sel.RS):
 186                 # for M-Form shiftrot
 187                 comb += self.reg_out.data.eq(self.dec.RS)
 188                 comb += self.reg_out.ok.eq(1)
 189             with m.Case(In2Sel.CONST_UI): # unsigned
 190                 comb += self.imm_out.data.eq(self.dec.UI)
 191                 comb += self.imm_out.ok.eq(1)
 192             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 193                 si = Signal(16, reset_less=True)
 194                 comb += si.eq(self.dec.SI)
 195                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 196                 comb += self.imm_out.ok.eq(1)
 197             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 198                 si_hi = Signal(32, reset_less=True)
 199                 comb += si_hi.eq(self.dec.SI << 16)
 200                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 201                 comb += self.imm_out.ok.eq(1)
 202             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 203                 ui = Signal(16, reset_less=True)
 204                 comb += ui.eq(self.dec.UI)
 205                 comb += self.imm_out.data.eq(ui << 16)
 206                 comb += self.imm_out.ok.eq(1)
 207             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 208                 li = Signal(26, reset_less=True)
 209                 comb += li.eq(self.dec.LI << 2)
 210                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 211                 comb += self.imm_out.ok.eq(1)
 212             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 213                 bd = Signal(16, reset_less=True)
 214                 comb += bd.eq(self.dec.BD << 2)
 215                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 216                 comb += self.imm_out.ok.eq(1)
 217             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 218                 ds = Signal(16, reset_less=True)
 219                 comb += ds.eq(self.dec.DS << 2)
 220                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 221                 comb += self.imm_out.ok.eq(1)
 222             with m.Case(In2Sel.CONST_M1): # signed (-1)
 223                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 224                 comb += self.imm_out.ok.eq(1)
 225             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 226                 comb += self.imm_out.data.eq(self.dec.sh)
 227                 comb += self.imm_out.ok.eq(1)
 228             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 229                 comb += self.imm_out.data.eq(self.dec.SH32)
 230                 comb += self.imm_out.ok.eq(1)
 231
 232         # decode SPR2 based on instruction type
 233         op = self.dec.op
 234         # BCREG implicitly uses LR or TAR for 2nd reg
 235         # CTR however is already in fast_spr1 *not* 2.
 236         with m.If(op.internal_op == MicrOp.OP_BCREG):
 237             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 238             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 239             with m.If(~xo9):
 240                 comb += self.fast_out.data.eq(FastRegs.LR)
 241                 comb += self.fast_out.ok.eq(1)
 242             with m.Elif(xo5):
 243                 comb += self.fast_out.data.eq(FastRegs.TAR)
 244                 comb += self.fast_out.ok.eq(1)
 245
 246         return m
 247
 248
 249 class DecodeC(Elaboratable):
 250     """DecodeC from instruction
 251
 252     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 253     """
 254
 255     def __init__(self, dec):
 256         self.dec = dec
 257         self.sel_in = Signal(In3Sel, reset_less=True)
 258         self.insn_in = Signal(32, reset_less=True)
 259         self.reg_out = Data(5, "reg_c")
 260
 261     def elaborate(self, platform):
 262         m = Module()
 263         comb = m.d.comb
 264
 265         # select Register C field
 266         with m.Switch(self.sel_in):
 267             with m.Case(In3Sel.RB):
 268                 # for M-Form shiftrot
 269                 comb += self.reg_out.data.eq(self.dec.RB)
 270                 comb += self.reg_out.ok.eq(1)
 271             with m.Case(In3Sel.RS):
 272                 comb += self.reg_out.data.eq(self.dec.RS)
 273                 comb += self.reg_out.ok.eq(1)
 274
 275         return m
 276
 277
 278 class DecodeOut(Elaboratable):
 279     """DecodeOut from instruction
 280
 281     decodes output register RA, RT or SPR
 282     """
 283
 284     def __init__(self, dec):
 285         self.dec = dec
 286         self.sel_in = Signal(OutSel, reset_less=True)
 287         self.insn_in = Signal(32, reset_less=True)
 288         self.reg_out = Data(5, "reg_o")
 289         self.spr_out = Data(SPR, "spr_o")
 290         self.fast_out = Data(3, "fast_o")
 291
 292     def elaborate(self, platform):
 293         m = Module()
 294         comb = m.d.comb
 295         m.submodules.sprmap = sprmap = SPRMap()
 296         op = self.dec.op
 297
 298         # select Register out field
 299         with m.Switch(self.sel_in):
 300             with m.Case(OutSel.RT):
 301                 comb += self.reg_out.data.eq(self.dec.RT)
 302                 comb += self.reg_out.ok.eq(1)
 303             with m.Case(OutSel.RA):
 304                 comb += self.reg_out.data.eq(self.dec.RA)
 305                 comb += self.reg_out.ok.eq(1)
 306             with m.Case(OutSel.SPR):
 307                 spr = Signal(10, reset_less=True)
 308                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 309                 # TODO MTSPR 1st spr (fast)
 310                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 311                     with m.Switch(spr):
 312                         # fast SPRs
 313                         with m.Case(SPR.CTR.value):
 314                             comb += self.fast_out.data.eq(FastRegs.CTR)
 315                             comb += self.fast_out.ok.eq(1)
 316                         with m.Case(SPR.LR.value):
 317                             comb += self.fast_out.data.eq(FastRegs.LR)
 318                             comb += self.fast_out.ok.eq(1)
 319                         with m.Case(SPR.TAR.value):
 320                             comb += self.fast_out.data.eq(FastRegs.TAR)
 321                             comb += self.fast_out.ok.eq(1)
 322                         with m.Case(SPR.SRR0.value):
 323                             comb += self.fast_out.data.eq(FastRegs.SRR0)
 324                             comb += self.fast_out.ok.eq(1)
 325                         with m.Case(SPR.SRR1.value):
 326                             comb += self.fast_out.data.eq(FastRegs.SRR1)
 327                             comb += self.fast_out.ok.eq(1)
 328                         with m.Case(SPR.XER.value):
 329                             pass  # do nothing
 330                         # : map to internal SPR numbers
 331                         # XXX TODO: dec and tb not to go through mapping.
 332                         with m.Default():
 333                             comb += sprmap.spr_i.eq(spr)
 334                             comb += self.spr_out.data.eq(sprmap.spr_o)
 335                             comb += self.spr_out.ok.eq(1)
 336
 337         with m.Switch(op.internal_op):
 338
 339             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 340             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 341                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 342                     # constant: CTR
 343                     comb += self.fast_out.data.eq(FastRegs.CTR)
 344                     comb += self.fast_out.ok.eq(1)
 345
 346             # RFID 1st spr (fast)
 347             with m.Case(MicrOp.OP_RFID):
 348                 comb += self.fast_out.data.eq(FastRegs.SRR0)  # constant: SRR0
 349                 comb += self.fast_out.ok.eq(1)
 350
 351         return m
 352
 353
 354 class DecodeOut2(Elaboratable):
 355     """DecodeOut2 from instruction
 356
 357     decodes output registers
 358     """
 359
 360     def __init__(self, dec):
 361         self.dec = dec
 362         self.sel_in = Signal(OutSel, reset_less=True)
 363         self.lk = Signal(reset_less=True)
 364         self.insn_in = Signal(32, reset_less=True)
 365         self.reg_out = Data(5, "reg_o")
 366         self.fast_out = Data(3, "fast_o")
 367
 368     def elaborate(self, platform):
 369         m = Module()
 370         comb = m.d.comb
 371
 372         # update mode LD/ST uses read-reg A also as an output
 373         with m.If(self.dec.op.upd == LDSTMode.update):
 374             comb += self.reg_out.eq(self.dec.RA)
 375             comb += self.reg_out.ok.eq(1)
 376
 377         # B, BC or BCREG: potential implicit register (LR) output
 378         # these give bl, bcl, bclrl, etc.
 379         op = self.dec.op
 380         with m.Switch(op.internal_op):
 381
 382             # BC* implicit register (LR)
 383             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 384                 with m.If(self.lk):  # "link" mode
 385                     comb += self.fast_out.data.eq(FastRegs.LR)  # constant: LR
 386                     comb += self.fast_out.ok.eq(1)
 387
 388             # RFID 2nd spr (fast)
 389             with m.Case(MicrOp.OP_RFID):
 390                 comb += self.fast_out.data.eq(FastRegs.SRR1)  # constant: SRR1
 391                 comb += self.fast_out.ok.eq(1)
 392
 393         return m
 394
 395
 396 class DecodeRC(Elaboratable):
 397     """DecodeRc from instruction
 398
 399     decodes Record bit Rc
 400     """
 401
 402     def __init__(self, dec):
 403         self.dec = dec
 404         self.sel_in = Signal(RC, reset_less=True)
 405         self.insn_in = Signal(32, reset_less=True)
 406         self.rc_out = Data(1, "rc")
 407
 408     def elaborate(self, platform):
 409         m = Module()
 410         comb = m.d.comb
 411
 412         # select Record bit out field
 413         with m.Switch(self.sel_in):
 414             with m.Case(RC.RC):
 415                 comb += self.rc_out.data.eq(self.dec.Rc)
 416                 comb += self.rc_out.ok.eq(1)
 417             with m.Case(RC.ONE):
 418                 comb += self.rc_out.data.eq(1)
 419                 comb += self.rc_out.ok.eq(1)
 420             with m.Case(RC.NONE):
 421                 comb += self.rc_out.data.eq(0)
 422                 comb += self.rc_out.ok.eq(1)
 423
 424         return m
 425
 426
 427 class DecodeOE(Elaboratable):
 428     """DecodeOE from instruction
 429
 430     decodes OE field: uses RC decode detection which might not be good
 431
 432     -- For now, use "rc" in the decode table to decide whether oe exists.
 433     -- This is not entirely correct architecturally: For mulhd and
 434     -- mulhdu, the OE field is reserved. It remains to be seen what an
 435     -- actual POWER9 does if we set it on those instructions, for now we
 436     -- test that further down when assigning to the multiplier oe input.
 437     """
 438
 439     def __init__(self, dec):
 440         self.dec = dec
 441         self.sel_in = Signal(RC, reset_less=True)
 442         self.insn_in = Signal(32, reset_less=True)
 443         self.oe_out = Data(1, "oe")
 444
 445     def elaborate(self, platform):
 446         m = Module()
 447         comb = m.d.comb
 448         op = self.dec.op
 449
 450         with m.Switch(op.internal_op):
 451
 452             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 453             # also rotate
 454             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 455                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 456                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 457                         MicrOp.OP_EXTSWSLI):
 458                 pass
 459
 460             # all other ops decode OE field
 461             with m.Default():
 462                 # select OE bit out field
 463                 with m.Switch(self.sel_in):
 464                     with m.Case(RC.RC):
 465                         comb += self.oe_out.data.eq(self.dec.OE)
 466                         comb += self.oe_out.ok.eq(1)
 467
 468         return m
 469
 470
 471 class DecodeCRIn(Elaboratable):
 472     """Decodes input CR from instruction
 473
 474     CR indices - insn fields - (not the data *in* the CR) require only 3
 475     bits because they refer to CR0-CR7
 476     """
 477
 478     def __init__(self, dec):
 479         self.dec = dec
 480         self.sel_in = Signal(CRInSel, reset_less=True)
 481         self.insn_in = Signal(32, reset_less=True)
 482         self.cr_bitfield = Data(3, "cr_bitfield")
 483         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 484         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 485         self.whole_reg = Signal(reset_less=True)
 486
 487     def elaborate(self, platform):
 488         m = Module()
 489         comb = m.d.comb
 490
 491         comb += self.cr_bitfield.ok.eq(0)
 492         comb += self.cr_bitfield_b.ok.eq(0)
 493         comb += self.whole_reg.eq(0)
 494         with m.Switch(self.sel_in):
 495             with m.Case(CRInSel.NONE):
 496                 pass  # No bitfield activated
 497             with m.Case(CRInSel.CR0):
 498                 comb += self.cr_bitfield.data.eq(0)
 499                 comb += self.cr_bitfield.ok.eq(1)
 500             with m.Case(CRInSel.BI):
 501                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 502                 comb += self.cr_bitfield.ok.eq(1)
 503             with m.Case(CRInSel.BFA):
 504                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 505                 comb += self.cr_bitfield.ok.eq(1)
 506             with m.Case(CRInSel.BA_BB):
 507                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 508                 comb += self.cr_bitfield.ok.eq(1)
 509                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 510                 comb += self.cr_bitfield_b.ok.eq(1)
 511                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 512                 comb += self.cr_bitfield_o.ok.eq(1)
 513             with m.Case(CRInSel.BC):
 514                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 515                 comb += self.cr_bitfield.ok.eq(1)
 516             with m.Case(CRInSel.WHOLE_REG):
 517                 comb += self.whole_reg.eq(1)
 518
 519         return m
 520
 521
 522 class DecodeCROut(Elaboratable):
 523     """Decodes input CR from instruction
 524
 525     CR indices - insn fields - (not the data *in* the CR) require only 3
 526     bits because they refer to CR0-CR7
 527     """
 528
 529     def __init__(self, dec):
 530         self.dec = dec
 531         self.rc_in = Signal(reset_less=True)
 532         self.sel_in = Signal(CROutSel, reset_less=True)
 533         self.insn_in = Signal(32, reset_less=True)
 534         self.cr_bitfield = Data(3, "cr_bitfield")
 535         self.whole_reg = Signal(reset_less=True)
 536
 537     def elaborate(self, platform):
 538         m = Module()
 539         comb = m.d.comb
 540
 541         comb += self.cr_bitfield.ok.eq(0)
 542         comb += self.whole_reg.eq(0)
 543         with m.Switch(self.sel_in):
 544             with m.Case(CROutSel.NONE):
 545                 pass  # No bitfield activated
 546             with m.Case(CROutSel.CR0):
 547                 comb += self.cr_bitfield.data.eq(0)
 548                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 549             with m.Case(CROutSel.BF):
 550                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 551                 comb += self.cr_bitfield.ok.eq(1)
 552             with m.Case(CROutSel.BT):
 553                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 554                 comb += self.cr_bitfield.ok.eq(1)
 555             with m.Case(CROutSel.WHOLE_REG):
 556                 comb += self.whole_reg.eq(1)
 557
 558         return m
 559
 560
 561 class PowerDecode2(Elaboratable):
 562     """PowerDecode2: the main instruction decoder.
 563
 564     whilst PowerDecode is responsible for decoding the actual opcode, this
 565     module encapsulates further specialist, sparse information and
 566     expansion of fields that is inconvenient to have in the CSV files.
 567     for example: the encoding of the immediates, which are detected
 568     and expanded out to their full value from an annotated (enum)
 569     representation.
 570
 571     implicit register usage is also set up, here.  for example: OP_BC
 572     requires implicitly reading CTR, OP_RFID requires implicitly writing
 573     to SRR1 and so on.
 574
 575     in addition, PowerDecoder2 is responsible for detecting whether
 576     instructions are illegal (or privileged) or not, and instead of
 577     just leaving at that, *replacing* the instruction to execute with
 578     a suitable alternative (trap).
 579     """
 580
 581     def __init__(self, dec):
 582
 583         self.dec = dec
 584         self.e = Decode2ToExecute1Type()
 585
 586         # state information needed by the Decoder (TODO: this as a Record)
 587         self.state = CoreState("dec2")
 588
 589     def ports(self):
 590         return self.dec.ports() + self.e.ports()
 591
 592     def elaborate(self, platform):
 593         m = Module()
 594         comb = m.d.comb
 595         e_out, op, do_out = self.e, self.dec.op, self.e.do
 596         msr, cia = self.state.msr, self.state.pc
 597
 598         # fill in for a normal instruction (not an exception)
 599         # copy over if non-exception, non-privileged etc. is detected
 600         e = Decode2ToExecute1Type()
 601         do = e.do
 602
 603         # set up submodule decoders
 604         m.submodules.dec = self.dec
 605         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 606         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 607         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 608         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 609         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 610         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 611         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 612         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 613         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 614
 615         # copy instruction through...
 616         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
 617                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 618                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 619             comb += i.eq(self.dec.opcode_in)
 620
 621         # ...and subdecoders' input fields
 622         comb += dec_a.sel_in.eq(op.in1_sel)
 623         comb += dec_b.sel_in.eq(op.in2_sel)
 624         comb += dec_c.sel_in.eq(op.in3_sel)
 625         comb += dec_o.sel_in.eq(op.out_sel)
 626         comb += dec_o2.sel_in.eq(op.out_sel)
 627         comb += dec_o2.lk.eq(do.lk)
 628         comb += dec_rc.sel_in.eq(op.rc_sel)
 629         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 630         comb += dec_cr_in.sel_in.eq(op.cr_in)
 631         comb += dec_cr_out.sel_in.eq(op.cr_out)
 632         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 633
 634         # copy "state" over
 635         comb += do.msr.eq(msr)
 636         comb += do.cia.eq(cia)
 637
 638         # set up instruction, pick fn unit
 639         # no op: defaults to OP_ILLEGAL
 640         comb += do.insn_type.eq(op.internal_op)
 641         comb += do.fn_unit.eq(op.function_unit)
 642
 643         # registers a, b, c and out and out2 (LD/ST EA)
 644         comb += e.read_reg1.eq(dec_a.reg_out)
 645         comb += e.read_reg2.eq(dec_b.reg_out)
 646         comb += e.read_reg3.eq(dec_c.reg_out)
 647         comb += e.write_reg.eq(dec_o.reg_out)
 648         comb += e.write_ea.eq(dec_o2.reg_out)
 649         comb += do.imm_data.eq(dec_b.imm_out)  # immediate in RB (usually)
 650         comb += do.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 651
 652         # rc and oe out
 653         comb += do.rc.eq(dec_rc.rc_out)
 654         comb += do.oe.eq(dec_oe.oe_out)
 655
 656         # SPRs out
 657         comb += e.read_spr1.eq(dec_a.spr_out)
 658         comb += e.write_spr.eq(dec_o.spr_out)
 659
 660         # Fast regs out
 661         comb += e.read_fast1.eq(dec_a.fast_out)
 662         comb += e.read_fast2.eq(dec_b.fast_out)
 663         comb += e.write_fast1.eq(dec_o.fast_out)
 664         comb += e.write_fast2.eq(dec_o2.fast_out)
 665
 666         # condition registers (CR)
 667         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 668         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 669         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 670         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 671
 672         comb += do.read_cr_whole.eq(dec_cr_in.whole_reg)
 673         comb += do.write_cr_whole.eq(dec_cr_out.whole_reg)
 674         comb += do.write_cr0.eq(dec_cr_out.cr_bitfield.ok)
 675
 676         # decoded/selected instruction flags
 677         comb += do.data_len.eq(op.ldst_len)
 678         comb += do.invert_in.eq(op.inv_a)
 679         comb += do.invert_out.eq(op.inv_out)
 680         comb += do.input_carry.eq(op.cry_in)   # carry comes in
 681         comb += do.output_carry.eq(op.cry_out)  # carry goes out
 682         comb += do.is_32bit.eq(op.is_32b)
 683         comb += do.is_signed.eq(op.sgn)
 684         with m.If(op.lk):
 685             comb += do.lk.eq(self.dec.LK)  # XXX TODO: accessor
 686
 687         comb += do.byte_reverse.eq(op.br)
 688         comb += do.sign_extend.eq(op.sgn_ext)
 689         comb += do.ldst_mode.eq(op.upd)  # LD/ST mode (update, cache-inhibit)
 690
 691         # These should be removed eventually
 692         comb += do.input_cr.eq(op.cr_in)   # condition reg comes in
 693         comb += do.output_cr.eq(op.cr_out)  # condition reg goes in
 694
 695         # sigh this is exactly the sort of thing for which the
 696         # decoder is designed to not need.  MTSPR, MFSPR and others need
 697         # access to the XER bits.  however setting e.oe is not appropriate
 698         with m.If(op.internal_op == MicrOp.OP_MFSPR):
 699             comb += e.xer_in.eq(1)
 700         with m.If(op.internal_op == MicrOp.OP_MTSPR):
 701             comb += e.xer_out.eq(1)
 702
 703         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
 704         with m.If(op.internal_op == MicrOp.OP_TRAP):
 705             # *DO NOT* call self.trap here.  that would reset absolutely
 706             # rverything including destroying read of RA and RB.
 707             comb += do.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 708
 709         # TODO: get msr, then can do privileged instruction
 710         with m.If(instr_is_priv(m, op.internal_op, e.do.insn) & msr[MSR.PR]):
 711             # privileged instruction trap
 712             self.trap(m, TT.PRIV, 0x700)
 713
 714         # illegal instruction must redirect to trap. this is done by
 715         # *overwriting* the decoded instruction and starting again.
 716         # (note: the same goes for interrupts and for privileged operations,
 717         # just with different trapaddr and traptype)
 718         with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL):
 719             # illegal instruction trap
 720             self.trap(m, TT.ILLEG, 0x700)
 721
 722         # no exception, just copy things to the output
 723         with m.Else():
 724             comb += e_out.eq(e)
 725
 726         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
 727         # Note: OP_SC could actually be modified to just be a trap
 728         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
 729                   (do_out.insn_type == MicrOp.OP_SC)):
 730             # TRAP write fast1 = SRR0
 731             comb += e_out.write_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 732             comb += e_out.write_fast1.ok.eq(1)
 733             # TRAP write fast2 = SRR1
 734             comb += e_out.write_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 735             comb += e_out.write_fast2.ok.eq(1)
 736
 737         # RFID: needs to read SRR0/1
 738         with m.If(do_out.insn_type == MicrOp.OP_RFID):
 739             # TRAP read fast1 = SRR0
 740             comb += e_out.read_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 741             comb += e_out.read_fast1.ok.eq(1)
 742             # TRAP read fast2 = SRR1
 743             comb += e_out.read_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 744             comb += e_out.read_fast2.ok.eq(1)
 745
 746         return m
 747
 748     def trap(self, m, traptype, trapaddr):
 749         """trap: this basically "rewrites" the decoded instruction as a trap
 750         """
 751         comb = m.d.comb
 752         op, do, e = self.dec.op, self.e.do, self.e
 753         comb += e.eq(0)  # reset eeeeeverything
 754
 755         # start again
 756         comb += do.insn.eq(self.dec.opcode_in)
 757         comb += do.insn_type.eq(MicrOp.OP_TRAP)
 758         comb += do.fn_unit.eq(Function.TRAP)
 759         comb += do.trapaddr.eq(trapaddr >> 4)  # cut bottom 4 bits
 760         comb += do.traptype.eq(traptype)  # request type
 761         comb += do.msr.eq(self.state.msr)  # copy of MSR "state"
 762         comb += do.cia.eq(self.state.pc)  # copy of PC "state"
 763
 764
 765 def get_rdflags(e, cu):
 766     rdl = []
 767     for idx in range(cu.n_src):
 768         regfile, regname, _ = cu.get_in_spec(idx)
 769         rdflag, read = regspec_decode_read(e, regfile, regname)
 770         rdl.append(rdflag)
 771     print("rdflags", rdl)
 772     return Cat(*rdl)
 773
 774
 775 if __name__ == '__main__':
 776     pdecode = create_pdecode()
 777     dec2 = PowerDecode2(pdecode)
 778     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 779     with open("dec2.il", "w") as f:
 780         f.write(vl)