src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode_read
  13 from soc.decoder.power_regspec_map import regspec_decode_write
  14 from soc.decoder.power_decoder import create_pdecode
  15 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  16                                      CRInSel, CROutSel,
  17                                      LdstLen, In1Sel, In2Sel, In3Sel,
  18                                      OutSel, SPR, RC)
  19 from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
  20
  21 from soc.regfile.regfiles import FastRegs
  22
  23 # see traptype (and trap main_stage.py)
  24
  25 TT_FP = 1<<0
  26 TT_PRIV = 1<<1
  27 TT_TRAP = 1<<2
  28 TT_ADDR = 1<<3
  29
  30 def decode_spr_num(spr):
  31     return Cat(spr[5:10], spr[0:5])
  32
  33
  34 def instr_is_priv(m, op, insn):
  35     """determines if the instruction is privileged or not
  36     """
  37     comb = m.d.comb
  38     Signal = is_priv_insn(reset_less=True)
  39     with m.Switch(op):
  40         with m.Case(InternalOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
  41         with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
  42         with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
  43         with m.Case(InternalOp.OP_RFID)  : comb += is_priv_insn.eq(1)
  44         with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  45     with m.If(op == OP_MFSPR | op == OP_MTSPR):
  46         with m.If(insn[20]): # field XFX.spr[-1] i think
  47             comb += is_priv_insn.eq(1)
  48     return is_priv_insn
  49
  50
  51 class DecodeA(Elaboratable):
  52     """DecodeA from instruction
  53
  54     decodes register RA, whether immediate-zero, implicit and
  55     explicit CSRs
  56     """
  57
  58     def __init__(self, dec):
  59         self.dec = dec
  60         self.sel_in = Signal(In1Sel, reset_less=True)
  61         self.insn_in = Signal(32, reset_less=True)
  62         self.reg_out = Data(5, name="reg_a")
  63         self.immz_out = Signal(reset_less=True)
  64         self.spr_out = Data(10, "spr_a")
  65         self.fast_out = Data(3, "fast_a")
  66
  67     def elaborate(self, platform):
  68         m = Module()
  69         comb = m.d.comb
  70
  71         # select Register A field
  72         ra = Signal(5, reset_less=True)
  73         comb += ra.eq(self.dec.RA)
  74         with m.If((self.sel_in == In1Sel.RA) |
  75                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  76                    (ra != Const(0, 5)))):
  77             comb += self.reg_out.data.eq(ra)
  78             comb += self.reg_out.ok.eq(1)
  79
  80         # zero immediate requested
  81         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  82                   (self.reg_out.data == Const(0, 5))):
  83             comb += self.immz_out.eq(1)
  84
  85         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  86         with m.If(self.sel_in == In1Sel.RS):
  87             comb += self.reg_out.data.eq(self.dec.RS)
  88             comb += self.reg_out.ok.eq(1)
  89
  90         # decode Fast-SPR based on instruction type
  91         op = self.dec.op
  92         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  93         with m.If(op.internal_op == InternalOp.OP_BC):
  94             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  95                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  96                 comb += self.fast_out.ok.eq(1)
  97         with m.Elif(op.internal_op == InternalOp.OP_BCREG):
  98             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
  99             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 100             with m.If(xo9 & ~xo5):
 101                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 102                 comb += self.fast_out.ok.eq(1)
 103
 104         # MFSPR move from SPRs
 105         with m.If(op.internal_op == InternalOp.OP_MFSPR):
 106             spr = Signal(10, reset_less=True)
 107             comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 108             with m.Switch(spr):
 109                 # fast SPRs
 110                 with m.Case(SPR.CTR.value):
 111                     comb += self.fast_out.data.eq(FastRegs.CTR)
 112                     comb += self.fast_out.ok.eq(1)
 113                 with m.Case(SPR.LR.value):
 114                     comb += self.fast_out.data.eq(FastRegs.LR)
 115                     comb += self.fast_out.ok.eq(1)
 116                 with m.Case(SPR.TAR.value):
 117                     comb += self.fast_out.data.eq(FastRegs.TAR)
 118                     comb += self.fast_out.ok.eq(1)
 119                 with m.Case(SPR.SRR0.value):
 120                     comb += self.fast_out.data.eq(FastRegs.SRR0)
 121                     comb += self.fast_out.ok.eq(1)
 122                 with m.Case(SPR.SRR1.value):
 123                     comb += self.fast_out.data.eq(FastRegs.SRR1)
 124                     comb += self.fast_out.ok.eq(1)
 125                 with m.Case(SPR.XER.value):
 126                     pass # do nothing
 127                 # XXX TODO: map to internal SPR numbers
 128                 # XXX TODO: dec and tb not to go through mapping.
 129                 with m.Default():
 130                     comb += self.spr_out.data.eq(spr)
 131                     comb += self.spr_out.ok.eq(1)
 132
 133
 134         return m
 135
 136
 137 class DecodeB(Elaboratable):
 138     """DecodeB from instruction
 139
 140     decodes register RB, different forms of immediate (signed, unsigned),
 141     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 142     by industry-standard convention, "lane 2" is where fully-decoded
 143     immediates are muxed in.
 144     """
 145
 146     def __init__(self, dec):
 147         self.dec = dec
 148         self.sel_in = Signal(In2Sel, reset_less=True)
 149         self.insn_in = Signal(32, reset_less=True)
 150         self.reg_out = Data(5, "reg_b")
 151         self.imm_out = Data(64, "imm_b")
 152         self.fast_out = Data(3, "fast_b")
 153
 154     def elaborate(self, platform):
 155         m = Module()
 156         comb = m.d.comb
 157
 158         # select Register B field
 159         with m.Switch(self.sel_in):
 160             with m.Case(In2Sel.RB):
 161                 comb += self.reg_out.data.eq(self.dec.RB)
 162                 comb += self.reg_out.ok.eq(1)
 163             with m.Case(In2Sel.RS):
 164                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 165                 comb += self.reg_out.ok.eq(1)
 166             with m.Case(In2Sel.CONST_UI):
 167                 comb += self.imm_out.data.eq(self.dec.UI)
 168                 comb += self.imm_out.ok.eq(1)
 169             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 170                 comb += self.imm_out.data.eq(
 171                     exts(self.dec.SI, 16, 64))
 172                 comb += self.imm_out.ok.eq(1)
 173             with m.Case(In2Sel.CONST_UI_HI):
 174                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 175                 comb += self.imm_out.ok.eq(1)
 176             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 177                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 178                 comb += self.imm_out.data.eq(
 179                     exts(self.dec.SI << 16, 32, 64))
 180                 comb += self.imm_out.ok.eq(1)
 181             with m.Case(In2Sel.CONST_LI):
 182                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 183                 comb += self.imm_out.ok.eq(1)
 184             with m.Case(In2Sel.CONST_BD):
 185                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 186                 comb += self.imm_out.ok.eq(1)
 187             with m.Case(In2Sel.CONST_DS):
 188                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 189                 comb += self.imm_out.ok.eq(1)
 190             with m.Case(In2Sel.CONST_M1):
 191                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 192                 comb += self.imm_out.ok.eq(1)
 193             with m.Case(In2Sel.CONST_SH):
 194                 comb += self.imm_out.data.eq(self.dec.sh)
 195                 comb += self.imm_out.ok.eq(1)
 196             with m.Case(In2Sel.CONST_SH32):
 197                 comb += self.imm_out.data.eq(self.dec.SH32)
 198                 comb += self.imm_out.ok.eq(1)
 199
 200         # decode SPR2 based on instruction type
 201         op = self.dec.op
 202         # BCREG implicitly uses LR or TAR for 2nd reg
 203         # CTR however is already in fast_spr1 *not* 2.
 204         with m.If(op.internal_op == InternalOp.OP_BCREG):
 205             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
 206             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 207             with m.If(~xo9):
 208                 comb += self.fast_out.data.eq(FastRegs.LR)
 209                 comb += self.fast_out.ok.eq(1)
 210             with m.Elif(xo5):
 211                 comb += self.fast_out.data.eq(FastRegs.TAR)
 212                 comb += self.fast_out.ok.eq(1)
 213
 214         return m
 215
 216
 217 class DecodeC(Elaboratable):
 218     """DecodeC from instruction
 219
 220     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 221     """
 222
 223     def __init__(self, dec):
 224         self.dec = dec
 225         self.sel_in = Signal(In3Sel, reset_less=True)
 226         self.insn_in = Signal(32, reset_less=True)
 227         self.reg_out = Data(5, "reg_c")
 228
 229     def elaborate(self, platform):
 230         m = Module()
 231         comb = m.d.comb
 232
 233         # select Register C field
 234         with m.Switch(self.sel_in):
 235             with m.Case(In3Sel.RB):
 236                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 237                 comb += self.reg_out.ok.eq(1)
 238             with m.Case(In3Sel.RS):
 239                 comb += self.reg_out.data.eq(self.dec.RS)
 240                 comb += self.reg_out.ok.eq(1)
 241
 242         return m
 243
 244
 245 class DecodeOut(Elaboratable):
 246     """DecodeOut from instruction
 247
 248     decodes output register RA, RT or SPR
 249     """
 250
 251     def __init__(self, dec):
 252         self.dec = dec
 253         self.sel_in = Signal(OutSel, reset_less=True)
 254         self.insn_in = Signal(32, reset_less=True)
 255         self.reg_out = Data(5, "reg_o")
 256         self.spr_out = Data(10, "spr_o")
 257         self.fast_out = Data(3, "fast_o")
 258
 259     def elaborate(self, platform):
 260         m = Module()
 261         comb = m.d.comb
 262         op = self.dec.op
 263
 264         # select Register out field
 265         with m.Switch(self.sel_in):
 266             with m.Case(OutSel.RT):
 267                 comb += self.reg_out.data.eq(self.dec.RT)
 268                 comb += self.reg_out.ok.eq(1)
 269             with m.Case(OutSel.RA):
 270                 comb += self.reg_out.data.eq(self.dec.RA)
 271                 comb += self.reg_out.ok.eq(1)
 272             with m.Case(OutSel.SPR):
 273                 spr = Signal(10, reset_less=True)
 274                 comb += spr.eq(decode_spr_num(self.dec.SPR)) # from XFX
 275                 # TODO MTSPR 1st spr (fast)
 276                 with m.If(op.internal_op == InternalOp.OP_MTSPR):
 277                     with m.Switch(spr):
 278                         # fast SPRs
 279                         with m.Case(SPR.CTR.value):
 280                             comb += self.fast_out.data.eq(FastRegs.CTR)
 281                             comb += self.fast_out.ok.eq(1)
 282                         with m.Case(SPR.LR.value):
 283                             comb += self.fast_out.data.eq(FastRegs.LR)
 284                             comb += self.fast_out.ok.eq(1)
 285                         with m.Case(SPR.TAR.value):
 286                             comb += self.fast_out.data.eq(FastRegs.TAR)
 287                             comb += self.fast_out.ok.eq(1)
 288                         with m.Case(SPR.SRR0.value):
 289                             comb += self.fast_out.data.eq(FastRegs.SRR0)
 290                             comb += self.fast_out.ok.eq(1)
 291                         with m.Case(SPR.SRR1.value):
 292                             comb += self.fast_out.data.eq(FastRegs.SRR1)
 293                             comb += self.fast_out.ok.eq(1)
 294                         with m.Case(SPR.XER.value):
 295                             pass # do nothing
 296                         # XXX TODO: map to internal SPR numbers
 297                         # XXX TODO: dec and tb not to go through mapping.
 298                         with m.Default():
 299                             comb += self.spr_out.data.eq(spr)
 300                             comb += self.spr_out.ok.eq(1)
 301
 302         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 303         op = self.dec.op
 304         with m.If((op.internal_op == InternalOp.OP_BC) |
 305                   (op.internal_op == InternalOp.OP_BCREG)):
 306             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 307                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 308                 comb += self.fast_out.ok.eq(1)
 309
 310         # RFID 1st spr (fast)
 311         with m.If(op.internal_op == InternalOp.OP_RFID):
 312             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
 313             comb += self.fast_out.ok.eq(1)
 314
 315         # TRAP fast1 = SRR0
 316         with m.If(op.internal_op == InternalOp.OP_TRAP):
 317             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
 318             comb += self.fast_out.ok.eq(1)
 319
 320         return m
 321
 322
 323 class DecodeOut2(Elaboratable):
 324     """DecodeOut2 from instruction
 325
 326     decodes output registers
 327     """
 328
 329     def __init__(self, dec):
 330         self.dec = dec
 331         self.sel_in = Signal(OutSel, reset_less=True)
 332         self.lk = Signal(reset_less=True)
 333         self.insn_in = Signal(32, reset_less=True)
 334         self.reg_out = Data(5, "reg_o")
 335         self.fast_out = Data(3, "fast_o")
 336
 337     def elaborate(self, platform):
 338         m = Module()
 339         comb = m.d.comb
 340
 341         # update mode LD/ST uses read-reg A also as an output
 342         with m.If(self.dec.op.upd):
 343             comb += self.reg_out.eq(self.dec.RA)
 344             comb += self.reg_out.ok.eq(1)
 345
 346         # BC or BCREG: potential implicit register (LR) output
 347         op = self.dec.op
 348         with m.If((op.internal_op == InternalOp.OP_BC) |
 349                   (op.internal_op == InternalOp.OP_BCREG)):
 350             with m.If(self.lk): # "link" mode
 351                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 352                 comb += self.fast_out.ok.eq(1)
 353
 354         # RFID 2nd spr (fast)
 355         with m.If(op.internal_op == InternalOp.OP_RFID):
 356                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
 357                 comb += self.fast_out.ok.eq(1)
 358
 359         # TRAP fast2 = SRR1
 360         with m.If(op.internal_op == InternalOp.OP_TRAP):
 361             comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
 362             comb += self.fast_out.ok.eq(1)
 363
 364         return m
 365
 366
 367 class DecodeRC(Elaboratable):
 368     """DecodeRc from instruction
 369
 370     decodes Record bit Rc
 371     """
 372     def __init__(self, dec):
 373         self.dec = dec
 374         self.sel_in = Signal(RC, reset_less=True)
 375         self.insn_in = Signal(32, reset_less=True)
 376         self.rc_out = Data(1, "rc")
 377
 378     def elaborate(self, platform):
 379         m = Module()
 380         comb = m.d.comb
 381
 382         # select Record bit out field
 383         with m.Switch(self.sel_in):
 384             with m.Case(RC.RC):
 385                 comb += self.rc_out.data.eq(self.dec.Rc)
 386                 comb += self.rc_out.ok.eq(1)
 387             with m.Case(RC.ONE):
 388                 comb += self.rc_out.data.eq(1)
 389                 comb += self.rc_out.ok.eq(1)
 390             with m.Case(RC.NONE):
 391                 comb += self.rc_out.data.eq(0)
 392                 comb += self.rc_out.ok.eq(1)
 393
 394         return m
 395
 396
 397 class DecodeOE(Elaboratable):
 398     """DecodeOE from instruction
 399
 400     decodes OE field: uses RC decode detection which might not be good
 401
 402     -- For now, use "rc" in the decode table to decide whether oe exists.
 403     -- This is not entirely correct architecturally: For mulhd and
 404     -- mulhdu, the OE field is reserved. It remains to be seen what an
 405     -- actual POWER9 does if we set it on those instructions, for now we
 406     -- test that further down when assigning to the multiplier oe input.
 407     """
 408     def __init__(self, dec):
 409         self.dec = dec
 410         self.sel_in = Signal(RC, reset_less=True)
 411         self.insn_in = Signal(32, reset_less=True)
 412         self.oe_out = Data(1, "oe")
 413
 414     def elaborate(self, platform):
 415         m = Module()
 416         comb = m.d.comb
 417
 418         # select OE bit out field
 419         with m.Switch(self.sel_in):
 420             with m.Case(RC.RC):
 421                 comb += self.oe_out.data.eq(self.dec.OE)
 422                 comb += self.oe_out.ok.eq(1)
 423
 424         return m
 425
 426 class DecodeCRIn(Elaboratable):
 427     """Decodes input CR from instruction
 428
 429     CR indices - insn fields - (not the data *in* the CR) require only 3
 430     bits because they refer to CR0-CR7
 431     """
 432
 433     def __init__(self, dec):
 434         self.dec = dec
 435         self.sel_in = Signal(CRInSel, reset_less=True)
 436         self.insn_in = Signal(32, reset_less=True)
 437         self.cr_bitfield = Data(3, "cr_bitfield")
 438         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 439         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 440         self.whole_reg = Signal(reset_less=True)
 441
 442     def elaborate(self, platform):
 443         m = Module()
 444         comb = m.d.comb
 445
 446         comb += self.cr_bitfield.ok.eq(0)
 447         comb += self.cr_bitfield_b.ok.eq(0)
 448         comb += self.whole_reg.eq(0)
 449         with m.Switch(self.sel_in):
 450             with m.Case(CRInSel.NONE):
 451                 pass # No bitfield activated
 452             with m.Case(CRInSel.CR0):
 453                 comb += self.cr_bitfield.data.eq(0)
 454                 comb += self.cr_bitfield.ok.eq(1)
 455             with m.Case(CRInSel.BI):
 456                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 457                 comb += self.cr_bitfield.ok.eq(1)
 458             with m.Case(CRInSel.BFA):
 459                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 460                 comb += self.cr_bitfield.ok.eq(1)
 461             with m.Case(CRInSel.BA_BB):
 462                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 463                 comb += self.cr_bitfield.ok.eq(1)
 464                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 465                 comb += self.cr_bitfield_b.ok.eq(1)
 466                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 467                 comb += self.cr_bitfield_o.ok.eq(1)
 468             with m.Case(CRInSel.BC):
 469                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 470                 comb += self.cr_bitfield.ok.eq(1)
 471             with m.Case(CRInSel.WHOLE_REG):
 472                 comb += self.whole_reg.eq(1)
 473
 474         return m
 475
 476
 477 class DecodeCROut(Elaboratable):
 478     """Decodes input CR from instruction
 479
 480     CR indices - insn fields - (not the data *in* the CR) require only 3
 481     bits because they refer to CR0-CR7
 482     """
 483
 484     def __init__(self, dec):
 485         self.dec = dec
 486         self.rc_in = Signal(reset_less=True)
 487         self.sel_in = Signal(CROutSel, reset_less=True)
 488         self.insn_in = Signal(32, reset_less=True)
 489         self.cr_bitfield = Data(3, "cr_bitfield")
 490         self.whole_reg = Signal(reset_less=True)
 491
 492     def elaborate(self, platform):
 493         m = Module()
 494         comb = m.d.comb
 495
 496         comb += self.cr_bitfield.ok.eq(0)
 497         comb += self.whole_reg.eq(0)
 498         with m.Switch(self.sel_in):
 499             with m.Case(CROutSel.NONE):
 500                 pass # No bitfield activated
 501             with m.Case(CROutSel.CR0):
 502                 comb += self.cr_bitfield.data.eq(0)
 503                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 504             with m.Case(CROutSel.BF):
 505                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 506                 comb += self.cr_bitfield.ok.eq(1)
 507             with m.Case(CROutSel.BT):
 508                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 509                 comb += self.cr_bitfield.ok.eq(1)
 510             with m.Case(CROutSel.WHOLE_REG):
 511                 comb += self.whole_reg.eq(1)
 512
 513         return m
 514
 515
 516 class XerBits:
 517     def __init__(self):
 518         self.ca = Signal(2, reset_less=True)
 519         self.ov = Signal(2, reset_less=True)
 520         self.so = Signal(reset_less=True)
 521
 522     def ports(self):
 523         return [self.ca, self.ov, self.so]
 524
 525
 526 class PowerDecode2(Elaboratable):
 527
 528     def __init__(self, dec):
 529
 530         self.dec = dec
 531         self.e = Decode2ToExecute1Type()
 532
 533     def ports(self):
 534         return self.dec.ports() + self.e.ports()
 535
 536     def elaborate(self, platform):
 537         m = Module()
 538         comb = m.d.comb
 539         e, op = self.e, self.dec.op
 540
 541         # set up submodule decoders
 542         m.submodules.dec = self.dec
 543         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 544         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 545         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 546         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 547         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 548         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 549         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 550         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 551         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 552
 553         # copy instruction through...
 554         for i in [e.insn, dec_a.insn_in, dec_b.insn_in,
 555                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 556                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 557             comb += i.eq(self.dec.opcode_in)
 558
 559         # ...and subdecoders' input fields
 560         comb += dec_a.sel_in.eq(op.in1_sel)
 561         comb += dec_b.sel_in.eq(op.in2_sel)
 562         comb += dec_c.sel_in.eq(op.in3_sel)
 563         comb += dec_o.sel_in.eq(op.out_sel)
 564         comb += dec_o2.sel_in.eq(op.out_sel)
 565         comb += dec_o2.lk.eq(e.lk)
 566         comb += dec_rc.sel_in.eq(op.rc_sel)
 567         comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
 568         comb += dec_cr_in.sel_in.eq(op.cr_in)
 569         comb += dec_cr_out.sel_in.eq(op.cr_out)
 570         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 571
 572
 573         comb += e.nia.eq(0)    # XXX TODO (or remove? not sure yet)
 574         fu = op.function_unit
 575         itype = Mux(fu == Function.NONE, InternalOp.OP_ILLEGAL, op.internal_op)
 576         comb += e.insn_type.eq(itype)
 577         comb += e.fn_unit.eq(fu)
 578
 579         # registers a, b, c and out and out2 (LD/ST EA)
 580         comb += e.read_reg1.eq(dec_a.reg_out)
 581         comb += e.read_reg2.eq(dec_b.reg_out)
 582         comb += e.read_reg3.eq(dec_c.reg_out)
 583         comb += e.write_reg.eq(dec_o.reg_out)
 584         comb += e.write_ea.eq(dec_o2.reg_out)
 585         comb += e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 586         comb += e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 587
 588         # rc and oe out
 589         comb += e.rc.eq(dec_rc.rc_out)
 590         comb += e.oe.eq(dec_oe.oe_out)
 591
 592         # SPRs out
 593         comb += e.read_spr1.eq(dec_a.spr_out)
 594         comb += e.write_spr.eq(dec_o.spr_out)
 595
 596         # Fast regs out
 597         comb += e.read_fast1.eq(dec_a.fast_out)
 598         comb += e.read_fast2.eq(dec_b.fast_out)
 599         comb += e.write_fast1.eq(dec_o.fast_out)
 600         comb += e.write_fast2.eq(dec_o2.fast_out)
 601
 602         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 603         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 604         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 605         comb += e.read_cr_whole.eq(dec_cr_in.whole_reg)
 606
 607         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 608         comb += e.write_cr_whole.eq(dec_cr_out.whole_reg)
 609
 610         # decoded/selected instruction flags
 611         comb += e.data_len.eq(op.ldst_len)
 612         comb += e.invert_a.eq(op.inv_a)
 613         comb += e.invert_out.eq(op.inv_out)
 614         comb += e.input_carry.eq(op.cry_in)   # carry comes in
 615         comb += e.output_carry.eq(op.cry_out) # carry goes out
 616         comb += e.is_32bit.eq(op.is_32b)
 617         comb += e.is_signed.eq(op.sgn)
 618         with m.If(op.lk):
 619             comb += e.lk.eq(self.dec.LK) # XXX TODO: accessor
 620
 621         comb += e.byte_reverse.eq(op.br)
 622         comb += e.sign_extend.eq(op.sgn_ext)
 623         comb += e.update.eq(op.upd) # LD/ST "update" mode.
 624
 625
 626         # These should be removed eventually
 627         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
 628         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 629
 630         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
 631         with m.If(op.internal_op == InternalOp.OP_TRAP):
 632             comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 633
 634         return m
 635
 636         # privileged instruction
 637         with m.If(instr_is_priv(m, op.internal_op, e.insn) & msr[MSR_PR]):
 638             # don't request registers RA/RT
 639             comb += e.read_reg1.eq(0)
 640             comb += e.read_reg2.eq(0)
 641             comb += e.read_reg3.eq(0)
 642             comb += e.write_reg.eq(0)
 643             comb += e.write_ea.eq(0)
 644             # privileged instruction trap
 645             comb += op.internal_op.eq(InternalOp.OP_TRAP)
 646             comb += e.traptype.eq(TT_PRIV) # request privileged instruction
 647             comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 648         return m
 649
 650     def regspecmap_read(self, regfile, regname):
 651         """regspecmap_read: provides PowerDecode2 with an encoding relationship
 652         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 653         regfile and regname arguments are fields 1 and 2 from a given regspec.
 654         """
 655         return regspec_decode_read(self.e, regfile, regname)
 656
 657     def regspecmap_write(self, regfile, regname):
 658         """regspecmap_write: provides PowerDecode2 with an encoding relationship
 659         to Function Unit port regfiles (write port, write regnum)
 660         regfile and regname arguments are fields 1 and 2 from a given regspec.
 661         """
 662         return regspec_decode_write(self.e, regfile, regname)
 663
 664     def rdflags(self, cu):
 665         rdl = []
 666         for idx in range(cu.n_src):
 667             regfile, regname, _ = cu.get_in_spec(idx)
 668             rdflag, read = self.regspecmap_read(regfile, regname)
 669             rdl.append(rdflag)
 670         print ("rdflags", rdl)
 671         return Cat(*rdl)
 672
 673
 674 if __name__ == '__main__':
 675     pdecode = create_pdecode()
 676     dec2 = PowerDecode2(pdecode)
 677     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 678     with open("dec2.il", "w") as f:
 679         f.write(vl)
 680