abad12910f70b5f30a88fd807e30257a9e3c86e8
1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import MSR
32 from soc
.regfile
.regfiles
import FastRegs
33 from soc
.consts
import TT
34 from soc
.config
.state
import CoreState
35 from soc
.regfile
.util
import spr_to_fast
38 def decode_spr_num(spr
):
39 return Cat(spr
[5:10], spr
[0:5])
42 def instr_is_priv(m
, op
, insn
):
43 """determines if the instruction is privileged or not
46 is_priv_insn
= Signal(reset_less
=True)
48 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
49 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
50 comb
+= is_priv_insn
.eq(1)
52 #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
53 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
54 with m
.If(insn
[20]): # field XFX.spr[-1] i think
55 comb
+= is_priv_insn
.eq(1)
59 class SPRMap(Elaboratable
):
60 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
64 self
.spr_i
= Signal(10, reset_less
=True)
65 self
.spr_o
= Data(SPR
, name
="spr_o")
66 self
.fast_o
= Data(3, name
="fast_o")
68 def elaborate(self
, platform
):
70 with m
.Switch(self
.spr_i
):
71 for i
, x
in enumerate(SPR
):
73 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
74 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
75 for x
, v
in spr_to_fast
.items():
77 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
78 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
82 class SVP64ExtraSpec(Elaboratable
):
83 """SVP64ExtraSpec - decodes SVP64 Extra specification.
85 selects the required EXTRA2/3 field.
87 see https://libre-soc.org/openpower/sv/svp64/
90 self
.extra
= Signal(10, reset_less
=True)
91 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
92 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
93 self
.spec
= Signal(3) # EXTRA spec for the register
95 def elaborate(self
, platform
):
100 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
101 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
102 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
103 # the register-extension information. extract those now
104 with m
.Switch(self
.etype
):
105 # 2-bit index selection mode
106 with m
.Case(SVEtype
.EXTRA2
):
107 with m
.Switch(self
.idx
):
108 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits
109 comb
+= spec
[1:3].eq(self
.extra
[0:2])
110 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits
111 comb
+= spec
[1:3].eq(self
.extra
[2:4])
112 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits
113 comb
+= spec
[1:3].eq(self
.extra
[4:6])
114 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits
115 comb
+= spec
[1:3].eq(self
.extra
[6:8])
116 # 3-bit index selection mode
117 with m
.Case(SVEtype
.EXTRA3
):
118 with m
.Switch(self
.idx
):
119 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits
120 comb
+= spec
.eq(self
.extra
[0:3])
121 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits
122 comb
+= spec
.eq(self
.extra
[3:6])
123 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits
124 comb
+= spec
.eq(self
.extra
[6:9])
125 # cannot fit more than 9 bits so there is no 4th thing
130 class SVP64RegExtra(SVP64ExtraSpec
):
131 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
133 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
134 depending on info in one of the positions in the EXTRA field.
136 designed so that "no change" to the 5-bit register number occurs if
137 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
139 see https://libre-soc.org/openpower/sv/svp64/
142 SVP64ExtraSpec
.__init
__(self
)
143 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
144 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
145 self
.isvec
= Signal(1) # reg is marked as vector if true
147 def elaborate(self
, platform
):
148 m
= super().elaborate(platform
) # select required EXTRA2/3
151 # first get the spec. if not changed it's "scalar identity behaviour"
152 # which is zero which is ok.
155 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
156 # from above, which (by design) has the effect of "no change", below.
158 # simple: isvec is top bit of spec
159 comb
+= self
.isvec
.eq(spec
[2])
161 # decode vector differently from scalar
162 with m
.If(self
.isvec
):
163 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
164 comb
+= self
.reg_out
.eq(Cat(spec
[:2], self
.reg_in
))
166 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
167 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec
[:2]))
172 class SVP64CRExtra(SVP64ExtraSpec
):
173 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
175 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
176 depending on info in one of the positions in the EXTRA field.
178 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
180 designed so that "no change" to the 3-bit CR register number occurs if
181 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
183 see https://libre-soc.org/openpower/sv/svp64/appendix
186 SVP64ExtraSpec
.__init
__(self
)
187 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
188 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
189 self
.isvec
= Signal(1) # reg is marked as vector if true
191 def elaborate(self
, platform
):
192 m
= super().elaborate(platform
) # select required EXTRA2/3
195 # first get the spec. if not changed it's "scalar identity behaviour"
196 # which is zero which is ok.
199 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
200 # from above, which (by design) has the effect of "no change", below.
202 # simple: isvec is top bit of spec
203 comb
+= self
.isvec
.eq(spec
[2])
205 # decode vector differently from scalar, insert bits 0 and 1 accordingly
206 with m
.If(self
.isvec
):
207 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
208 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec
[:2], self
.cr_in
))
210 # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
211 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec
[:2]))
216 class DecodeA(Elaboratable
):
217 """DecodeA from instruction
219 decodes register RA, implicit and explicit CSRs
222 def __init__(self
, dec
):
224 self
.sv_rm
= SVP64Rec() # SVP64 RM field
225 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
226 self
.insn_in
= Signal(32, reset_less
=True)
227 self
.reg_out
= Data(7, name
="reg_a")
228 self
.reg_isvec
= Signal(1, name
="reg_a_isvec") # TODO: in reg_out
229 self
.spr_out
= Data(SPR
, "spr_a")
230 self
.fast_out
= Data(3, "fast_a")
232 def elaborate(self
, platform
):
236 m
.submodules
.sprmap
= sprmap
= SPRMap()
237 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
239 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
240 reg
= Signal(5, reset_less
=True)
242 # select Register A field
243 ra
= Signal(5, reset_less
=True)
244 comb
+= ra
.eq(self
.dec
.RA
)
245 with m
.If((self
.sel_in
== In1Sel
.RA
) |
246 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
247 (ra
!= Const(0, 5)))):
249 comb
+= self
.reg_out
.ok
.eq(1)
251 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
252 # moved it to 1st position (in1_sel)... because
253 rs
= Signal(5, reset_less
=True)
254 comb
+= rs
.eq(self
.dec
.RS
)
255 with m
.If(self
.sel_in
== In1Sel
.RS
):
257 comb
+= self
.reg_out
.ok
.eq(1)
259 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
260 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
261 # which in turn were auto-generated by sv_analysis.py
263 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
264 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
265 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
266 comb
+= svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
267 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
269 # outputs: 7-bit reg number and whether it's vectorised
270 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
271 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
273 # decode Fast-SPR based on instruction type
274 with m
.Switch(op
.internal_op
):
276 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
277 with m
.Case(MicrOp
.OP_BC
):
278 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
280 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
281 comb
+= self
.fast_out
.ok
.eq(1)
282 with m
.Case(MicrOp
.OP_BCREG
):
283 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
284 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
285 with m
.If(xo9
& ~xo5
):
287 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
288 comb
+= self
.fast_out
.ok
.eq(1)
290 # MFSPR move from SPRs
291 with m
.Case(MicrOp
.OP_MFSPR
):
292 spr
= Signal(10, reset_less
=True)
293 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
294 comb
+= sprmap
.spr_i
.eq(spr
)
295 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
296 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
301 class DecodeAImm(Elaboratable
):
302 """DecodeA immediate from instruction
304 decodes register RA, whether immediate-zero, implicit and
308 def __init__(self
, dec
):
310 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
311 self
.immz_out
= Signal(reset_less
=True)
313 def elaborate(self
, platform
):
317 # zero immediate requested
318 ra
= Signal(5, reset_less
=True)
319 comb
+= ra
.eq(self
.dec
.RA
)
320 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
321 comb
+= self
.immz_out
.eq(1)
326 class DecodeB(Elaboratable
):
327 """DecodeB from instruction
329 decodes register RB, different forms of immediate (signed, unsigned),
330 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
331 by industry-standard convention, "lane 2" is where fully-decoded
332 immediates are muxed in.
335 def __init__(self
, dec
):
337 self
.sv_rm
= SVP64Rec() # SVP64 RM field
338 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
339 self
.insn_in
= Signal(32, reset_less
=True)
340 self
.reg_out
= Data(7, "reg_b")
341 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
342 self
.fast_out
= Data(3, "fast_b")
344 def elaborate(self
, platform
):
348 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
350 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
351 reg
= Signal(5, reset_less
=True)
353 # select Register B field
354 with m
.Switch(self
.sel_in
):
355 with m
.Case(In2Sel
.RB
):
356 comb
+= reg
.eq(self
.dec
.RB
)
357 comb
+= self
.reg_out
.ok
.eq(1)
358 with m
.Case(In2Sel
.RS
):
359 # for M-Form shiftrot
360 comb
+= reg
.eq(self
.dec
.RS
)
361 comb
+= self
.reg_out
.ok
.eq(1)
363 # now do the SVP64 munging. different from DecodeA only by sv_in2
365 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
366 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
367 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
368 comb
+= svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
369 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
371 # outputs: 7-bit reg number and whether it's vectorised
372 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
373 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
375 # decode SPR2 based on instruction type
376 # BCREG implicitly uses LR or TAR for 2nd reg
377 # CTR however is already in fast_spr1 *not* 2.
378 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
379 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
380 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
382 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
383 comb
+= self
.fast_out
.ok
.eq(1)
385 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
386 comb
+= self
.fast_out
.ok
.eq(1)
391 class DecodeBImm(Elaboratable
):
392 """DecodeB immediate from instruction
394 def __init__(self
, dec
):
396 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
397 self
.imm_out
= Data(64, "imm_b")
399 def elaborate(self
, platform
):
403 # select Register B Immediate
404 with m
.Switch(self
.sel_in
):
405 with m
.Case(In2Sel
.CONST_UI
): # unsigned
406 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
407 comb
+= self
.imm_out
.ok
.eq(1)
408 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
409 si
= Signal(16, reset_less
=True)
410 comb
+= si
.eq(self
.dec
.SI
)
411 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
412 comb
+= self
.imm_out
.ok
.eq(1)
413 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
414 si_hi
= Signal(32, reset_less
=True)
415 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
416 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
417 comb
+= self
.imm_out
.ok
.eq(1)
418 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
419 ui
= Signal(16, reset_less
=True)
420 comb
+= ui
.eq(self
.dec
.UI
)
421 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
422 comb
+= self
.imm_out
.ok
.eq(1)
423 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
424 li
= Signal(26, reset_less
=True)
425 comb
+= li
.eq(self
.dec
.LI
<< 2)
426 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
427 comb
+= self
.imm_out
.ok
.eq(1)
428 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
429 bd
= Signal(16, reset_less
=True)
430 comb
+= bd
.eq(self
.dec
.BD
<< 2)
431 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
432 comb
+= self
.imm_out
.ok
.eq(1)
433 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
434 ds
= Signal(16, reset_less
=True)
435 comb
+= ds
.eq(self
.dec
.DS
<< 2)
436 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
437 comb
+= self
.imm_out
.ok
.eq(1)
438 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
439 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
440 comb
+= self
.imm_out
.ok
.eq(1)
441 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
442 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
443 comb
+= self
.imm_out
.ok
.eq(1)
444 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
445 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
446 comb
+= self
.imm_out
.ok
.eq(1)
451 class DecodeC(Elaboratable
):
452 """DecodeC from instruction
454 decodes register RC. this is "lane 3" into some CompUnits (not many)
457 def __init__(self
, dec
):
459 self
.sv_rm
= SVP64Rec() # SVP64 RM field
460 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
461 self
.insn_in
= Signal(32, reset_less
=True)
462 self
.reg_out
= Data(7, "reg_c")
463 self
.reg_isvec
= Signal(1, name
="reg_c_isvec") # TODO: in reg_out
465 def elaborate(self
, platform
):
469 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
471 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
472 reg
= Signal(5, reset_less
=True)
474 # select Register C field
475 with m
.Switch(self
.sel_in
):
476 with m
.Case(In3Sel
.RB
):
477 # for M-Form shiftrot
478 comb
+= reg
.eq(self
.dec
.RB
)
479 comb
+= self
.reg_out
.ok
.eq(1)
480 with m
.Case(In3Sel
.RS
):
481 comb
+= reg
.eq(self
.dec
.RS
)
482 comb
+= self
.reg_out
.ok
.eq(1)
484 # now do the SVP64 munging. different from DecodeA only by sv_in3
486 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
487 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
488 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
489 comb
+= svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
490 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
492 # outputs: 7-bit reg number and whether it's vectorised
493 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
494 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
499 class DecodeOut(Elaboratable
):
500 """DecodeOut from instruction
502 decodes output register RA, RT or SPR
505 def __init__(self
, dec
):
507 self
.sv_rm
= SVP64Rec() # SVP64 RM field
508 self
.sel_in
= Signal(OutSel
, reset_less
=True)
509 self
.insn_in
= Signal(32, reset_less
=True)
510 self
.reg_out
= Data(7, "reg_o")
511 self
.reg_isvec
= Signal(1, name
="reg_o_isvec") # TODO: in reg_out
512 self
.spr_out
= Data(SPR
, "spr_o")
513 self
.fast_out
= Data(3, "fast_o")
515 def elaborate(self
, platform
):
518 m
.submodules
.sprmap
= sprmap
= SPRMap()
520 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
522 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
523 reg
= Signal(5, reset_less
=True)
525 # select Register out field
526 with m
.Switch(self
.sel_in
):
527 with m
.Case(OutSel
.RT
):
528 comb
+= reg
.eq(self
.dec
.RT
)
529 comb
+= self
.reg_out
.ok
.eq(1)
530 with m
.Case(OutSel
.RA
):
531 comb
+= reg
.eq(self
.dec
.RA
)
532 comb
+= self
.reg_out
.ok
.eq(1)
533 with m
.Case(OutSel
.SPR
):
534 spr
= Signal(10, reset_less
=True)
535 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
536 # MFSPR move to SPRs - needs mapping
537 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
538 comb
+= sprmap
.spr_i
.eq(spr
)
539 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
540 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
542 # now do the SVP64 munging. different from DecodeA only by sv_out
544 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
545 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
546 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
547 comb
+= svdec
.idx
.eq(op
.sv_out
) # SVP64 reg out1 (matches out_sel)
548 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
550 # outputs: 7-bit reg number and whether it's vectorised
551 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
552 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
555 with m
.Switch(op
.internal_op
):
557 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
558 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
559 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
561 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
562 comb
+= self
.fast_out
.ok
.eq(1)
564 # RFID 1st spr (fast)
565 with m
.Case(MicrOp
.OP_RFID
):
566 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
567 comb
+= self
.fast_out
.ok
.eq(1)
572 class DecodeOut2(Elaboratable
):
573 """DecodeOut2 from instruction
575 decodes output registers (2nd one). note that RA is *implicit* below,
576 which now causes problems with SVP64
578 TODO: SVP64 is a little more complex, here. svp64 allows extending
579 by one more destination by having one more EXTRA field. RA-as-src
580 is not the same as RA-as-dest. limited in that it's the same first
581 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
582 for operations that have src-as-dest: mostly this is LD/ST-with-update
583 but there are others.
586 def __init__(self
, dec
):
588 self
.sv_rm
= SVP64Rec() # SVP64 RM field
589 self
.sel_in
= Signal(OutSel
, reset_less
=True)
590 self
.lk
= Signal(reset_less
=True)
591 self
.insn_in
= Signal(32, reset_less
=True)
592 self
.reg_out
= Data(7, "reg_o2")
593 #self.reg_isvec = Signal(1, name="reg_o2_isvec") # TODO: in reg_out
594 self
.fast_out
= Data(3, "fast_o2")
596 def elaborate(self
, platform
):
600 #m.submodules.svdec = svdec = SVP64RegExtra()
602 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
603 #reg = Signal(5, reset_less=True)
605 if hasattr(self
.dec
.op
, "upd"):
606 # update mode LD/ST uses read-reg A also as an output
607 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
608 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
609 comb
+= self
.reg_out
.ok
.eq(1)
611 # B, BC or BCREG: potential implicit register (LR) output
612 # these give bl, bcl, bclrl, etc.
613 with m
.Switch(op
.internal_op
):
615 # BC* implicit register (LR)
616 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
617 with m
.If(self
.lk
): # "link" mode
618 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
619 comb
+= self
.fast_out
.ok
.eq(1)
621 # RFID 2nd spr (fast)
622 with m
.Case(MicrOp
.OP_RFID
):
623 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
624 comb
+= self
.fast_out
.ok
.eq(1)
629 class DecodeRC(Elaboratable
):
630 """DecodeRc from instruction
632 decodes Record bit Rc
635 def __init__(self
, dec
):
637 self
.sel_in
= Signal(RC
, reset_less
=True)
638 self
.insn_in
= Signal(32, reset_less
=True)
639 self
.rc_out
= Data(1, "rc")
641 def elaborate(self
, platform
):
645 # select Record bit out field
646 with m
.Switch(self
.sel_in
):
648 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
649 comb
+= self
.rc_out
.ok
.eq(1)
651 comb
+= self
.rc_out
.data
.eq(1)
652 comb
+= self
.rc_out
.ok
.eq(1)
653 with m
.Case(RC
.NONE
):
654 comb
+= self
.rc_out
.data
.eq(0)
655 comb
+= self
.rc_out
.ok
.eq(1)
660 class DecodeOE(Elaboratable
):
661 """DecodeOE from instruction
663 decodes OE field: uses RC decode detection which might not be good
665 -- For now, use "rc" in the decode table to decide whether oe exists.
666 -- This is not entirely correct architecturally: For mulhd and
667 -- mulhdu, the OE field is reserved. It remains to be seen what an
668 -- actual POWER9 does if we set it on those instructions, for now we
669 -- test that further down when assigning to the multiplier oe input.
672 def __init__(self
, dec
):
674 self
.sel_in
= Signal(RC
, reset_less
=True)
675 self
.insn_in
= Signal(32, reset_less
=True)
676 self
.oe_out
= Data(1, "oe")
678 def elaborate(self
, platform
):
683 with m
.Switch(op
.internal_op
):
685 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
687 # XXX ARGH! ignoring OE causes incompatibility with microwatt
688 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
689 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
690 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
691 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
692 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
693 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
697 # all other ops decode OE field
699 # select OE bit out field
700 with m
.Switch(self
.sel_in
):
702 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
703 comb
+= self
.oe_out
.ok
.eq(1)
708 class DecodeCRIn(Elaboratable
):
709 """Decodes input CR from instruction
711 CR indices - insn fields - (not the data *in* the CR) require only 3
712 bits because they refer to CR0-CR7
715 def __init__(self
, dec
):
717 self
.sv_rm
= SVP64Rec() # SVP64 RM field
718 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
719 self
.insn_in
= Signal(32, reset_less
=True)
720 self
.cr_bitfield
= Data(3, "cr_bitfield")
721 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
722 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
723 self
.whole_reg
= Data(8, "cr_fxm")
725 def elaborate(self
, platform
):
727 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
732 m
.submodules
.svdec
= svdec
= SVP64CRExtra()
733 m
.submodules
.svdec_b
= svdec_b
= SVP64CRExtra()
734 m
.submodules
.svdec_o
= svdec_o
= SVP64CRExtra()
736 comb
+= self
.cr_bitfield
.ok
.eq(0)
737 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
738 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
739 comb
+= self
.whole_reg
.ok
.eq(0)
741 with m
.Switch(self
.sel_in
):
742 with m
.Case(CRInSel
.NONE
):
743 pass # No bitfield activated
744 with m
.Case(CRInSel
.CR0
):
745 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
746 comb
+= self
.cr_bitfield
.ok
.eq(1)
747 with m
.Case(CRInSel
.BI
):
748 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
749 comb
+= self
.cr_bitfield
.ok
.eq(1)
750 with m
.Case(CRInSel
.BFA
):
751 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
752 comb
+= self
.cr_bitfield
.ok
.eq(1)
753 with m
.Case(CRInSel
.BA_BB
):
754 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
755 comb
+= self
.cr_bitfield
.ok
.eq(1)
756 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
757 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
758 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
759 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
760 with m
.Case(CRInSel
.BC
):
761 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
762 comb
+= self
.cr_bitfield
.ok
.eq(1)
763 with m
.Case(CRInSel
.WHOLE_REG
):
764 comb
+= self
.whole_reg
.ok
.eq(1)
765 move_one
= Signal(reset_less
=True)
766 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
767 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
768 # must one-hot the FXM field
769 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
770 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
772 # otherwise use all of it
773 comb
+= self
.whole_reg
.data
.eq(0xff)
778 class DecodeCROut(Elaboratable
):
779 """Decodes input CR from instruction
781 CR indices - insn fields - (not the data *in* the CR) require only 3
782 bits because they refer to CR0-CR7
785 def __init__(self
, dec
):
787 self
.sv_rm
= SVP64Rec() # SVP64 RM field
788 self
.rc_in
= Signal(reset_less
=True)
789 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
790 self
.insn_in
= Signal(32, reset_less
=True)
791 self
.cr_bitfield
= Data(3, "cr_bitfield")
792 self
.whole_reg
= Data(8, "cr_fxm")
794 def elaborate(self
, platform
):
798 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
801 comb
+= self
.cr_bitfield
.ok
.eq(0)
802 comb
+= self
.whole_reg
.ok
.eq(0)
803 with m
.Switch(self
.sel_in
):
804 with m
.Case(CROutSel
.NONE
):
805 pass # No bitfield activated
806 with m
.Case(CROutSel
.CR0
):
807 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
808 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
809 with m
.Case(CROutSel
.BF
):
810 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
811 comb
+= self
.cr_bitfield
.ok
.eq(1)
812 with m
.Case(CROutSel
.BT
):
813 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
814 comb
+= self
.cr_bitfield
.ok
.eq(1)
815 with m
.Case(CROutSel
.WHOLE_REG
):
816 comb
+= self
.whole_reg
.ok
.eq(1)
817 move_one
= Signal(reset_less
=True)
818 comb
+= move_one
.eq(self
.insn_in
[20])
819 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
821 # must one-hot the FXM field
822 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
823 with m
.If(ppick
.en_o
):
824 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
826 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
828 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
830 # otherwise use all of it
831 comb
+= self
.whole_reg
.data
.eq(0xff)
835 # dictionary of Input Record field names that, if they exist,
836 # will need a corresponding CSV Decoder file column (actually, PowerOp)
837 # to be decoded (this includes the single bit names)
838 record_names
= {'insn_type': 'internal_op',
839 'fn_unit': 'function_unit',
843 'imm_data': 'in2_sel',
844 'invert_in': 'inv_a',
845 'invert_out': 'inv_out',
848 'output_carry': 'cry_out',
849 'input_carry': 'cry_in',
850 'is_32bit': 'is_32b',
853 'data_len': 'ldst_len',
854 'byte_reverse': 'br',
855 'sign_extend': 'sgn_ext',
860 class PowerDecodeSubset(Elaboratable
):
861 """PowerDecodeSubset: dynamic subset decoder
863 only fields actually requested are copied over. hence, "subset" (duh).
865 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
867 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
870 self
.fn_name
= fn_name
872 opkls
= Decode2ToOperand
873 self
.do
= opkls(fn_name
)
874 col_subset
= self
.get_col_subset(self
.do
)
876 # only needed for "main" PowerDecode2
878 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
880 # create decoder if one not already given
882 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
883 row_subset
=self
.rowsubsetfn
)
886 # state information needed by the Decoder
888 state
= CoreState("dec2")
891 def get_col_subset(self
, do
):
892 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
893 for k
, v
in record_names
.items():
896 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
899 def rowsubsetfn(self
, opcode
, row
):
900 return row
['unit'] == self
.fn_name
903 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
905 def needs_field(self
, field
, op_field
):
910 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
912 def do_copy(self
, field
, val
, final
=False):
913 if final
or self
.final
:
917 if hasattr(do
, field
) and val
is not None:
918 return getattr(do
, field
).eq(val
)
921 def op_get(self
, op_field
):
922 return getattr(self
.dec
.op
, op_field
, None)
924 def elaborate(self
, platform
):
928 op
, do
= self
.dec
.op
, self
.do
929 msr
, cia
= state
.msr
, state
.pc
931 # fill in for a normal instruction (not an exception)
932 # copy over if non-exception, non-privileged etc. is detected
934 if self
.fn_name
is None:
937 name
= self
.fn_name
+ "tmp"
938 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
940 # set up submodule decoders
941 m
.submodules
.dec
= self
.dec
942 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
943 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
944 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
945 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
947 # copy instruction through...
949 dec_rc
.insn_in
, dec_oe
.insn_in
,
950 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
951 comb
+= i
.eq(self
.dec
.opcode_in
)
953 # ...and subdecoders' input fields
954 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
955 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
956 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
957 comb
+= self
.dec_cr_in
.sv_rm
.eq(self
.sv_rm
)
958 comb
+= self
.dec_cr_out
.sv_rm
.eq(self
.sv_rm
)
959 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
960 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
963 comb
+= self
.do_copy("msr", msr
)
964 comb
+= self
.do_copy("cia", cia
)
966 # set up instruction type
967 # no op: defaults to OP_ILLEGAL
968 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
970 # function unit for decoded instruction: requires minor redirect
972 fn
= self
.op_get("function_unit")
973 spr
= Signal(10, reset_less
=True)
974 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
976 # for first test only forward SPRs 18 and 19 to MMU, when
977 # operation is MTSPR or MFSPR. TODO: add other MMU SPRs
978 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
979 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
980 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
))):
981 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
983 comb
+= self
.do_copy("fn_unit",fn
)
986 if self
.needs_field("zero_a", "in1_sel"):
987 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
988 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
989 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
990 if self
.needs_field("imm_data", "in2_sel"):
991 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
992 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
993 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
996 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
997 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
1000 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
1001 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
1002 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
1004 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
1005 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
1007 # decoded/selected instruction flags
1008 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
1009 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
1010 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
1011 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
1012 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
1013 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
1014 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
1015 lk
= self
.op_get("lk")
1018 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
1020 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
1021 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
1022 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
1027 class PowerDecode2(PowerDecodeSubset
):
1028 """PowerDecode2: the main instruction decoder.
1030 whilst PowerDecode is responsible for decoding the actual opcode, this
1031 module encapsulates further specialist, sparse information and
1032 expansion of fields that is inconvenient to have in the CSV files.
1033 for example: the encoding of the immediates, which are detected
1034 and expanded out to their full value from an annotated (enum)
1037 implicit register usage is also set up, here. for example: OP_BC
1038 requires implicitly reading CTR, OP_RFID requires implicitly writing
1041 in addition, PowerDecoder2 is responsible for detecting whether
1042 instructions are illegal (or privileged) or not, and instead of
1043 just leaving at that, *replacing* the instruction to execute with
1044 a suitable alternative (trap).
1046 LDSTExceptions are done the cycle _after_ they're detected (after
1047 they come out of LDSTCompUnit). basically despite the instruction
1048 being decoded, the results of the decode are completely ignored
1049 and "exception.happened" used to set the "actual" instruction to
1050 "OP_TRAP". the LDSTException data structure gets filled in,
1051 in the CompTrapOpSubset and that's what it fills in SRR.
1053 to make this work, TestIssuer must notice "exception.happened"
1054 after the (failed) LD/ST and copies the LDSTException info from
1055 the output, into here (PowerDecoder2). without incrementing PC.
1058 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
1059 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
1060 self
.exc
= LDSTException("dec2_exc")
1062 def get_col_subset(self
, opkls
):
1063 subset
= super().get_col_subset(opkls
)
1064 subset
.add("asmcode")
1065 subset
.add("in1_sel")
1066 subset
.add("in2_sel")
1067 subset
.add("in3_sel")
1068 subset
.add("out_sel")
1069 subset
.add("sv_in1")
1070 subset
.add("sv_in2")
1071 subset
.add("sv_in3")
1072 subset
.add("sv_out")
1073 subset
.add("SV_Etype")
1074 subset
.add("SV_Ptype")
1076 subset
.add("internal_op")
1080 def elaborate(self
, platform
):
1081 m
= super().elaborate(platform
)
1084 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1085 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1089 # fill in for a normal instruction (not an exception)
1090 # copy over if non-exception, non-privileged etc. is detected
1092 # set up submodule decoders
1093 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1094 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1095 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1096 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1097 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1099 # copy instruction through...
1100 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1101 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1102 comb
+= i
.eq(self
.dec
.opcode_in
)
1105 for i
in [dec_a
.insn_in
, dec_b
.insn_in
,
1106 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1107 comb
+= i
.eq(self
.sv_rm
)
1109 # ...and subdecoders' input fields
1110 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1111 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1112 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1113 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1114 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1115 if hasattr(do
, "lk"):
1116 comb
+= dec_o2
.lk
.eq(do
.lk
)
1118 # registers a, b, c and out and out2 (LD/ST EA)
1119 for to_reg
, fromreg
in (
1120 (e
.read_reg1
, dec_a
.reg_out
),
1121 (e
.read_reg2
, dec_b
.reg_out
),
1122 (e
.read_reg3
, dec_c
.reg_out
),
1123 (e
.write_reg
, dec_o
.reg_out
),
1124 (e
.write_ea
, dec_o2
.reg_out
)):
1125 comb
+= to_reg
.data
.eq(fromreg
.data
)
1126 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1129 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1130 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1133 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1134 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1135 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1136 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1138 # condition registers (CR)
1139 for to_reg
, fromreg
in (
1140 (e
.read_cr1
, self
.dec_cr_in
.cr_bitfield
),
1141 (e
.read_cr2
, self
.dec_cr_in
.cr_bitfield_b
),
1142 (e
.read_cr3
, self
.dec_cr_in
.cr_bitfield_o
),
1143 (e
.write_cr
, self
.dec_cr_out
.cr_bitfield
)):
1144 comb
+= to_reg
.data
.eq(fromreg
.data
)
1145 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1147 # sigh this is exactly the sort of thing for which the
1148 # decoder is designed to not need. MTSPR, MFSPR and others need
1149 # access to the XER bits. however setting e.oe is not appropriate
1150 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1151 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1152 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1153 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1154 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1155 comb
+= e
.xer_out
.eq(1)
1157 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1158 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1159 # *DO NOT* call self.trap here. that would reset absolutely
1160 # everything including destroying read of RA and RB.
1161 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1163 ####################
1164 # ok so the instruction's been decoded, blah blah, however
1165 # now we need to determine if it's actually going to go ahead...
1166 # *or* if in fact it's a privileged operation, whether there's
1167 # an external interrupt, etc. etc. this is a simple priority
1168 # if-elif-elif sequence. decrement takes highest priority,
1169 # EINT next highest, privileged operation third.
1171 # check if instruction is privileged
1172 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1174 # different IRQ conditions
1175 ext_irq_ok
= Signal()
1176 dec_irq_ok
= Signal()
1181 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1182 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1183 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1184 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1186 # LD/ST exceptions. TestIssuer copies the exception info at us
1187 # after a failed LD/ST.
1188 with m
.If(exc
.happened
):
1189 with m
.If(exc
.alignment
):
1190 self
.trap(m
, TT
.PRIV
, 0x600)
1191 with m
.Elif(exc
.instr_fault
):
1192 with m
.If(exc
.segment_fault
):
1193 self
.trap(m
, TT
.PRIV
, 0x480)
1195 # pass exception info to trap to create SRR1
1196 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1198 with m
.If(exc
.segment_fault
):
1199 self
.trap(m
, TT
.PRIV
, 0x380)
1201 self
.trap(m
, TT
.PRIV
, 0x300)
1203 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1204 with m
.Elif(dec_irq_ok
):
1205 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1207 # external interrupt? only if MSR.EE set
1208 with m
.Elif(ext_irq_ok
):
1209 self
.trap(m
, TT
.EINT
, 0x500)
1211 # privileged instruction trap
1212 with m
.Elif(priv_ok
):
1213 self
.trap(m
, TT
.PRIV
, 0x700)
1215 # illegal instruction must redirect to trap. this is done by
1216 # *overwriting* the decoded instruction and starting again.
1217 # (note: the same goes for interrupts and for privileged operations,
1218 # just with different trapaddr and traptype)
1219 with m
.Elif(illeg_ok
):
1220 # illegal instruction trap
1221 self
.trap(m
, TT
.ILLEG
, 0x700)
1223 # no exception, just copy things to the output
1227 ####################
1228 # follow-up after trap/irq to set up SRR0/1
1230 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1231 # Note: OP_SC could actually be modified to just be a trap
1232 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1233 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1234 # TRAP write fast1 = SRR0
1235 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1236 comb
+= e_out
.write_fast1
.ok
.eq(1)
1237 # TRAP write fast2 = SRR1
1238 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1239 comb
+= e_out
.write_fast2
.ok
.eq(1)
1241 # RFID: needs to read SRR0/1
1242 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1243 # TRAP read fast1 = SRR0
1244 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1245 comb
+= e_out
.read_fast1
.ok
.eq(1)
1246 # TRAP read fast2 = SRR1
1247 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1248 comb
+= e_out
.read_fast2
.ok
.eq(1)
1250 # annoying simulator bug
1251 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1252 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1256 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1257 """trap: this basically "rewrites" the decoded instruction as a trap
1260 op
, e
= self
.dec
.op
, self
.e
1261 comb
+= e
.eq(0) # reset eeeeeverything
1264 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1265 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1266 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1267 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1268 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1269 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1270 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1271 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1274 def get_rdflags(e
, cu
):
1276 for idx
in range(cu
.n_src
):
1277 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1278 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1280 print("rdflags", rdl
)
1284 if __name__
== '__main__':
1285 pdecode
= create_pdecode()
1286 dec2
= PowerDecode2(pdecode
)
1287 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1288 with
open("dec2.il", "w") as f
: