test_ldst_pi.py: fix race condition causing early stop

[soc.git] / Makefile

diff --git a/Makefile b/Makefile
index b7d73ee58c280d298136d9773db7bffa972747c9..909a463a0d605f97d2c931c5e65015ca1d1b1406 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -13,11 +13,13 @@ mkpinmux:
 
 install: gitupdate develop mkpinmux svanalysis
 
+# this is now actually part of openpower-isa repository
 pywriter:
-       python3 src/soc/decoder/pseudo/pywriter.py
+       pywriter
 
+# this is now actually part of openpower-isa repository
 svanalysis:
-       python3 libreriscv/openpower/sv_analysis.py
+       svanalysis
 
 develop:
        python3 setup.py develop # yes, develop, not install
@@ -36,6 +38,12 @@ testgpio_run_sim:
        python3 src/soc/litex/florent/sim.py --cpu=libresoc \
                        --variant=standardjtagtestgpio
 
+ls180_verilog_nopll:
+       python3 src/soc/simple/issuer_verilog.py \
+               --debug=jtag --enable-core --disable-pll \
+               --enable-xics --disable-svp64 \
+                       src/soc/litex/florent/libresoc/libresoc.v
+
 ls180_verilog:
        python3 src/soc/simple/issuer_verilog.py \
                --debug=jtag --enable-core --enable-pll \
@@ -49,8 +57,8 @@ ls180_4k_verilog:
                        src/soc/litex/florent/libresoc/libresoc.v
 
 # build the litex libresoc SoC without 4k SRAMs
-ls180_4ksram_verilog_build: ls180_verilog
-       make -C soc/soc/litex/florent ls1804k
+ls180_verilog_build: ls180_verilog
+       make -C soc/soc/litex/florent ls180
 
 # build the litex libresoc SoC with 4k SRAMs
 ls180_4ksram_verilog_build: ls180_4k_verilog
@@ -60,6 +68,9 @@ ls180_4ksram_verilog_build: ls180_4k_verilog
 test: install
        python3 setup.py test # could just run nosetest3...
 
+pypiupload:
+       $(PYTHON3) setup.py sdist upload
+
 # Minimal makefile for Sphinx documentation
 #