add JTAG enable/disable of wishbone to TestIssuer

[soc.git] / README.md

diff --git a/README.md b/README.md
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--- a/README.md
+++ b/README.md
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+# About
+The main SOC portion of Libre-SOC. A quad-core open source SOC with a GPU, VPU, and
+open source VLSI design cells.
+
+Open source down to VLSI Cells.
+
+# [Documentation](https://libre-soc.org/Documentation/index/)
+
 # Installation
 
-python3 setup.py develop
+    make update
+    make install
+    make test # optional (ish)
 
 # Running Simulator tests