use register-based DepCell

[soc.git] / src / experiment / compalu.py

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index b4df27e5181a9193599ef4bd3cc834bba5eee5cb..d03a8d2cbfdf342065b8d71b508e2bbdc1c18178 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -54,7 +54,7 @@ class ComputationUnitNoDelay(Elaboratable):
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 
         with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
-            m.d.sync += self.counter.eq(5)
+            m.d.sync += self.counter.eq(3)
         with m.If(self.counter > 0):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If((self.counter == 1) | (self.counter == 0)):