self.go_rd_i = Signal(n_units, reset_less=True)
self.go_wr_i = Signal(n_units, reset_less=True)
self.busy_o = Signal(n_units, reset_less=True)
+ self.rd_rel_o = Signal(n_units, reset_less=True)
self.req_rel_o = Signal(n_units, reset_less=True)
self.dest_o = Signal(rwid, reset_less=True)
# Int ALUs
add = ALU(self.rwid)
sub = ALU(self.rwid)
- m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
- m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
- int_alus = [comp1, comp2]
-
- m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
- m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
+ mul = ALU(self.rwid)
+ shf = ALU(self.rwid)
+ m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 2, add)
+ m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 2, sub)
+ m.submodules.comp3 = comp3 = ComputationUnitNoDelay(self.rwid, 2, mul)
+ m.submodules.comp4 = comp4 = ComputationUnitNoDelay(self.rwid, 2, shf)
+ int_alus = [comp1, comp2, comp3, comp4]
+
+ m.d.comb += comp1.oper_i.eq(Const(0, 2)) # op=add
+ m.d.comb += comp2.oper_i.eq(Const(1, 2)) # op=sub
+ m.d.comb += comp3.oper_i.eq(Const(2, 2)) # op=mul
+ m.d.comb += comp4.oper_i.eq(Const(3, 2)) # op=shf
go_rd_l = []
go_wr_l = []
issue_l = []
busy_l = []
req_rel_l = []
+ rd_rel_l = []
for alu in int_alus:
req_rel_l.append(alu.req_rel_o)
+ rd_rel_l.append(alu.rd_rel_o)
go_wr_l.append(alu.go_wr_i)
go_rd_l.append(alu.go_rd_i)
issue_l.append(alu.issue_i)
busy_l.append(alu.busy_o)
+ m.d.comb += self.rd_rel_o.eq(Cat(*rd_rel_l))
m.d.comb += self.req_rel_o.eq(Cat(*req_rel_l))
m.d.comb += self.busy_o.eq(Cat(*busy_l))
m.d.comb += Cat(*go_wr_l).eq(self.go_wr_i)
self.src1_i = Signal(n_regs, reset_less=True) # oper1 R# in
self.src2_i = Signal(n_regs, reset_less=True) # oper2 R# in
+ self.g_int_rd_pend_o = Signal(n_regs, reset_less=True)
+ self.g_int_wr_pend_o = Signal(n_regs, reset_less=True)
+
self.dest_rsel_o = Signal(n_regs, reset_less=True) # dest reg (bot)
self.src1_rsel_o = Signal(n_regs, reset_less=True) # src1 reg (bot)
self.src2_rsel_o = Signal(n_regs, reset_less=True) # src2 reg (bot)
self.req_rel_i = Signal(n_int_alus, reset_less = True)
- self.g_int_rd_pend_o = Signal(n_regs, reset_less=True)
- self.g_int_wr_pend_o = Signal(n_regs, reset_less=True)
self.readable_o = Signal(n_int_alus, reset_less=True)
self.writable_o = Signal(n_int_alus, reset_less=True)
intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
m.submodules.intregdeps = intregdeps
- m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_pend_o)
- m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_pend_o)
+ m.d.comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o)
+ m.d.comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o)
- m.d.sync += intfudeps.rd_pend_i.eq(self.g_int_rd_pend_o)
- m.d.sync += intfudeps.wr_pend_i.eq(self.g_int_wr_pend_o)
+ m.d.comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o)
+ m.d.comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o)
+
+ m.d.comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o)
+ m.d.comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o)
m.d.comb += intfudeps.issue_i.eq(self.fn_issue_i)
m.d.comb += intfudeps.go_rd_i.eq(self.go_rd_i)
self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
+ self.reg_enable_i = Signal(reset_less=True) # enable reg decode
self.issue_o = Signal(reset_less=True) # instruction was accepted
fp_src2 = self.fpregs.read_port("src2")
# Int ALUs and Comp Units
- n_int_alus = 2
+ n_int_alus = 4
m.submodules.cu = cu = CompUnits(self.rwid, n_int_alus)
# Int FUs
n_fp_fus = 0 # for now
# Integer Priority Picker 1: Adder + Subtractor
- intpick1 = GroupPicker(2) # picks between add and sub
+ intpick1 = GroupPicker(n_int_fus) # picks between add, sub, mul and shf
m.submodules.intpick1 = intpick1
# INT/FP Issue Unit
regdecode.dest_i.eq(self.int_dest_i),
regdecode.src1_i.eq(self.int_src1_i),
regdecode.src2_i.eq(self.int_src2_i),
- regdecode.enable_i.eq(1),
+ regdecode.enable_i.eq(self.reg_enable_i),
issueunit.i.dest_i.eq(regdecode.dest_o),
self.issue_o.eq(issueunit.issue_o)
]
m.d.comb += intfus.fn_issue_i.eq(fn_issue_o)
# XXX sync, so as to stop a simulation infinite loop
- m.d.sync += issueunit.i.busy_i.eq(cu.busy_o)
+ m.d.comb += issueunit.i.busy_i.eq(cu.busy_o)
#---------
# connect fu-fu matrix
go_wr_o = intpick1.go_wr_o
go_rd_i = intfus.go_rd_i
go_wr_i = intfus.go_wr_i
- m.d.comb += go_rd_i[0:2].eq(go_rd_o[0:2]) # add rd
- m.d.comb += go_wr_i[0:2].eq(go_wr_o[0:2]) # add wr
+ m.d.comb += go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus]) # rd
+ m.d.comb += go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus]) # wr
# Connect Picker
#---------
- m.d.comb += intpick1.req_rel_i[0:2].eq(cu.req_rel_o[0:2])
- int_readable_o = intfus.readable_o
- int_writable_o = intfus.writable_o
- m.d.comb += intpick1.readable_i[0:2].eq(int_readable_o[0:2])
- m.d.comb += intpick1.writable_i[0:2].eq(int_writable_o[0:2])
+ m.d.comb += intpick1.rd_rel_i[0:n_int_fus].eq(cu.rd_rel_o[0:n_int_fus])
+ m.d.comb += intpick1.req_rel_i[0:n_int_fus].eq(cu.req_rel_o[0:n_int_fus])
+ int_rd_o = intfus.readable_o
+ int_wr_o = intfus.writable_o
+ m.d.comb += intpick1.readable_i[0:n_int_fus].eq(int_rd_o[0:n_int_fus])
+ m.d.comb += intpick1.writable_i[0:n_int_fus].eq(int_wr_o[0:n_int_fus])
#---------
# Connect Register File(s)
#---------
print ("intregdeps wen len", len(intfus.dest_rsel_o))
- m.d.sync += int_dest.wen.eq(intfus.dest_rsel_o)
+ m.d.comb += int_dest.wen.eq(intfus.dest_rsel_o)
m.d.comb += int_src1.ren.eq(intfus.src1_rsel_o)
m.d.comb += int_src2.ren.eq(intfus.src2_rsel_o)
m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
# connect ALU Computation Units
- m.d.sync += cu.go_rd_i[0:2].eq(go_rd_o[0:2])
- m.d.sync += cu.go_wr_i[0:2].eq(go_wr_o[0:2])
- m.d.sync += cu.issue_i[0:2].eq(fn_issue_o[0:2])
+ m.d.comb += cu.go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus])
+ m.d.comb += cu.go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus])
+ m.d.comb += cu.issue_i[0:n_int_fus].eq(fn_issue_o[0:n_int_fus])
return m
IADD = 0
ISUB = 1
+IMUL = 2
+ISHF = 3
class RegSim:
def __init__(self, rwidth, nregs):
src1 = self.regs[src1]
src2 = self.regs[src2]
if op == IADD:
- val = (src1 + src2) & ((1<<(self.rwidth))-1)
+ val = (src1 + src2)
elif op == ISUB:
- val = (src1 - src2) & ((1<<(self.rwidth))-1)
+ val = (src1 - src2)
+ elif op == IMUL:
+ val = (src1 * src2)
+ elif op == ISHF:
+ val = (src1 << (src2 & self.rwidth))
+ val &= ((1<<(self.rwidth))-1)
self.regs[dest] = val
def setval(self, dest, val):
yield dut.int_src1_i.eq(src1)
yield dut.int_src2_i.eq(src2)
yield dut.int_insn_i[op].eq(1)
+ yield dut.reg_enable_i.eq(1)
alusim.op(op, src1, src2, dest)
yield dut.int_store_i.eq(0)
for i in range(1, dut.n_regs):
- yield dut.intregs.regs[i].reg.eq(i*2)
- alusim.setval(i, i*2)
+ yield dut.intregs.regs[i].reg.eq(4+i*2)
+ alusim.setval(i, 4+i*2)
+
+ instrs = []
+ if True:
+ for i in range(200):
+ src1 = randint(1, dut.n_regs-1)
+ src2 = randint(1, dut.n_regs-1)
+ while True:
+ dest = randint(1, dut.n_regs-1)
+ if dest not in [src1, src2]:
+ break
+ #src1 = 2
+ #src2 = 3
+ #dest = 2
+
+ op = randint(0, 2)
+ #op = i % 2
+ #op = 0
+
+ instrs.append((src1, src2, dest, op))
if False:
- yield from int_instr(dut, alusim, IADD, 4, 3, 5)
- yield from print_reg(dut, [3,4,5])
- yield
- yield from int_instr(dut, alusim, IADD, 5, 2, 5)
- yield from print_reg(dut, [3,4,5])
- yield
- yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
- yield from print_reg(dut, [3,4,5])
- yield
- for i in range(len(dut.int_insn_i)):
- yield dut.int_insn_i[i].eq(0)
- yield from print_reg(dut, [3,4,5])
- yield
- yield from print_reg(dut, [3,4,5])
- yield
- yield from print_reg(dut, [3,4,5])
- yield
+ instrs.append((2, 3, 3, 0))
+ instrs.append((5, 3, 3, 1))
- yield from alusim.check(dut)
+ if False:
+ instrs.append((5, 6, 2, 1))
+ instrs.append((2, 2, 4, 0))
+ #instrs.append((2, 2, 3, 1))
- for i in range(5):
- src1 = randint(1, dut.n_regs-1)
- src2 = randint(1, dut.n_regs-1)
- while True:
- dest = randint(1, dut.n_regs-1)
- break
- if dest not in [src1, src2]:
- break
- #src1 = 7
- #src2 = 4
- #dest = 2
+ if False:
+ instrs.append((2, 1, 2, 3))
+
+ if False:
+ instrs.append((2, 6, 2, 1))
+ instrs.append((2, 1, 2, 0))
+
+ if False:
+ instrs.append((1, 2, 7, 2))
+ instrs.append((7, 1, 5, 0))
+ instrs.append((4, 4, 1, 1))
+
+ if False:
+ instrs.append((5, 6, 2, 2))
+ instrs.append((1, 1, 4, 1))
+ instrs.append((6, 5, 3, 0))
+
+ for i, (src1, src2, dest, op) in enumerate(instrs):
- op = randint(0, 1)
- op = 0
- print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
+ print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
yield from int_instr(dut, alusim, op, src1, src2, dest)
- yield from print_reg(dut, [3,4,5])
yield
- yield from print_reg(dut, [3,4,5])
- for i in range(len(dut.int_insn_i)):
- yield dut.int_insn_i[i].eq(0)
- yield
- yield
-
+ while True:
+ issue_o = yield dut.issue_o
+ if issue_o:
+ for i in range(len(dut.int_insn_i)):
+ yield dut.int_insn_i[i].eq(0)
+ yield dut.reg_enable_i.eq(0)
+ break
+ print ("busy",)
+ yield from print_reg(dut, [1,2,3])
+ yield
+ yield from print_reg(dut, [1,2,3])
yield
- yield from print_reg(dut, [3,4,5])
+ yield from print_reg(dut, [1,2,3])
+ yield
+ yield from print_reg(dut, [1,2,3])
+ yield
+ yield from print_reg(dut, [1,2,3])
yield
- yield from print_reg(dut, [3,4,5])
+ yield from print_reg(dut, [1,2,3])
yield
yield
yield
def test_scoreboard():
- dut = Scoreboard(32, 8)
- alusim = RegSim(32, 8)
+ dut = Scoreboard(16, 8)
+ alusim = RegSim(16, 8)
vl = rtlil.convert(dut, ports=dut.ports())
with open("test_scoreboard6600.il", "w") as f:
f.write(vl)
projects / soc.git / blobdiff