add in special regs to be passed out of function (as return results)

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 2d2f5bdcc78977ce74f10f08285576652307443d..558172bb61cf54664a99360969abec82075c7d1e 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -96,7 +96,9 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             sim = self.run_tst_program(program)
         print ("cr", sim.cr)
-        self.assertEqual(sim.cr, SelectableInt(0xffffffff, 32))
+        self.assertEqual(sim.cr, SelectableInt(0xf, 32))
+        print ("cr0", sim.crl[0])
+        self.assertTrue(SelectableInt(0xf, 4) == sim.crl[0])
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
         simulator = self.run_tst(prog, initial_regs)