Add test_mfcr

[soc.git] / src / soc / decoder / isa / test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 21364340e5395a27c2951a34d5ae63d8bb8964e8..78766f6c0d608556c6200ecfb5e76c71e55b9baf 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -128,8 +128,11 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
             self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
 
             self.assertEqual(sim.gpr(1), SelectableInt(0x1234, 64))
             self.assertEqual(sim.gpr(2), SelectableInt(0, 64))
 

-
-
+    def test_mfcr(self):
+        lst = ["mfcr 1"]
+        with Program(lst) as program:
+            sim = self.run_tst_program(program)
+            self.assertEqual(sim.gpr(1), SelectableInt(0, 64))

 
     def test_mtcrf(self):
         for i in range(4):
 
     def test_mtcrf(self):
         for i in range(4):