**FOR NOW** LD/ST relies on detection of twin-predication to determine

[soc.git] / src / soc / decoder / isa / test_caller_svp64.py

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 6441e1f5d9afe4a4ac1db9af3b382e7be6347306..7875dc089c638d717c5ea87c45288b837aaf4c93 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -26,8 +26,8 @@ class DecoderTestCase(FHDLTestCase):
                         "addi 2, 0, 0x0008",
                         "addi 5, 0, 0x1234",
                         "addi 6, 0, 0x1235",
-                        "sv.stw 5, 0(1)",
-                        "sv.lwz 9, 0(1)"])
+                        "sv.stw 5.v, 0(1.v)",
+                        "sv.lwz 9.v, 0(1.v)"])
         lst = list(lst)
 
         # SVSTATE (in this case, VL=2)
@@ -40,7 +40,7 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, svstate=svstate)
             print(sim.gpr(1))
             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
-            #self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
+            self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
 
     def test_sv_add(self):
         # adds: