Fix comment in CR predication test case

[soc.git] / src / soc / decoder / isa / test_caller_svp64_predication.py

diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index eed0b79c4c6b2d5f66f4f413df670f974f3acf81..20b7c278d2ba6760679df99fb97b0e81240e7ba6 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -173,8 +173,8 @@ class DecoderTestCase(FHDLTestCase):
         expected_regs[1] = 0xbeef
         expected_regs[2] = 0x3334
 
-        # set up CR predicate - CR4.eq=0 and CR5.eq=1
-        cr = (0b0010) << ((7-4)*4) # CR5.eq (we hope)
+        # set up CR predicate - CR4.eq=1 and CR5.eq=0
+        cr = (0b0010) << ((7-4)*4) # CR4.eq (we hope)
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate,