add INT, SPR and CR regfiles

[soc.git] / src / soc / decoder / power_enums.py

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 1895bce8d1cc5acf3c0e00118d5e2ef3fc744fa7..05e23f8e8ee1f0bddc412c48f1cc08bf6fe6b6de 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -161,6 +161,8 @@ class InternalOp(Enum):
     OP_SIM_CONFIG = 68
     OP_CROP = 69
     OP_RFID = 70
+    OP_MFMSR = 71
+    OP_MTMSRD = 72
 
 
 @unique
@@ -265,3 +267,11 @@ XER_bits = {
     'OV32': 44,
     'CA32': 45
     }
+
+if __name__ == '__main__':
+    # find out what the heck is in SPR enum :)
+    print ("sprs", len(SPR))
+    print (dir(SPR))
+    print (dir(Enum))
+    for x in SPR:
+        print (x, x.value)