move over to from openpower imports

[soc.git] / src / soc / experiment / compalu.py

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index 89d2da1a2c8c0210b0733d6a9c5b0f2ef634b92c..05539cd485ac833266595e23a92d7034c90d5d67 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -3,8 +3,8 @@ from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Mux, Elaboratable
 
 from nmutil.latch import SRLatch, latchregister
-from soc.decoder.power_decoder2 import Data
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_decoder2 import Data
+from openpower.decoder.power_enums import MicrOp
 
 from soc.experiment.alu_hier import CompALUOpSubset
 
@@ -224,7 +224,7 @@ def scoreboard_sim(dut):
 
 def test_scoreboard():
     from alu_hier import ALU
-    from soc.decoder.power_decoder2 import Decode2ToExecute1Type
+    from openpower.decoder.power_decoder2 import Decode2ToExecute1Type
 
     alu = ALU(16)
     dut = ComputationUnitNoDelay(16, alu)