adding immediates, tracking down a bug

[soc.git] / src / soc / experiment / compalu.py

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index 2be7ba6d5f6e20e20e8a80c204f67153be2e7ce2..d0fe6aa392103faea31878418ed801cc744e3a22 100644 (file)
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -112,7 +112,7 @@ class ComputationUnitNoDelay(Elaboratable):
         op_is_imm = self.imm_i.imm_ok
         src2_or_imm = Signal(self.rwid, reset_less=True)
         src_sel = Signal(reset_less=True)
-        m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.qn, src_l.q))
+        m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q))
         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i.imm, self.src2_i))
 
         # create a latch/register for src1/src2
@@ -167,7 +167,7 @@ class ComputationUnitNoDelay(Elaboratable):
         return list(self)
 
 
-def op_sim(dut, a, b, op, inv_a=0):
+def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)
@@ -176,6 +176,8 @@ def op_sim(dut, a, b, op, inv_a=0):
     yield dut.src2_i.eq(b)
     yield dut.oper_i.insn_type.eq(op)
     yield dut.oper_i.invert_a.eq(inv_a)
+    yield dut.imm_i.imm.eq(imm)
+    yield dut.imm_i.imm_ok.eq(imm_ok)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)
@@ -209,6 +211,10 @@ def op_sim(dut, a, b, op, inv_a=0):
 
 
 def scoreboard_sim(dut):
+    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
+                                    imm=8, imm_ok=1)
+    assert result == 13
+
     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
     assert result == 65532