bit of a big reorg of data structures

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 8db244a1569ba135a1d640af160e5bb3adf80ea9..d7e32f28c556e76aff9be146ce280eba9745bb09 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -165,7 +165,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # to trigger *from* the opcode latch instead.
         src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
         src_sel = Signal(reset_less=True)
-        m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, self.src_l.q[i]))
+        m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, sl[i][2]))
         m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
         # overwrite 1st src-latch with immediate-muxed stuff
         sl[i][0] = src_or_imm
@@ -233,12 +233,12 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
 
         # read-done,wr-proceed latch
-        m.d.comb += rok_l.s.eq(self.issue_i)  # set up when issue starts
+        m.d.sync += rok_l.s.eq(self.issue_i)  # set up when issue starts
         m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o)  # ALU done
 
         # wr-done, back-to-start latch
-        m.d.comb += rst_l.s.eq(all_rd)     # set when read-phase is fully done
-        m.d.comb += rst_l.r.eq(rst_r)        # *off* on issue
+        m.d.sync += rst_l.s.eq(all_rd)     # set when read-phase is fully done
+        m.d.sync += rst_l.r.eq(rst_r)        # *off* on issue
 
         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
         m.d.sync += opc_l.s.eq(self.issue_i)       # set on issue
@@ -249,7 +249,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.sync += src_l.r.eq(reset_r)
 
         # dest operand latch (not using issue_i)
-        m.d.comb += req_l.s.eq(alu_pulsem & self.wrmask)
+        m.d.sync += req_l.s.eq(alu_pulsem & self.wrmask)
         m.d.sync += req_l.r.eq(reset_w | prev_wr_go)
 
         # pass operation to the ALU (sync: plenty time to wait for src reads)
@@ -270,11 +270,14 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
                 # bye-bye abstract interface design..
                 fname = find_ok(data_r.fields)
                 if fname:
-                    ok = data_r[fname]
+                    ok = getattr(lro, fname)
             else:
                 data_r = Signal.like(lro, name=name, reset_less=True)
             wrok.append(ok & self.busy_o)
-            latchregister(m, lro, data_r, alu_pulsem, name + "_l")
+            with m.If(alu_pulse):
+                m.d.sync += data_r.eq(lro)
+            with m.If(self.issue_i):
+                m.d.sync += data_r.eq(0)
             drl.append(data_r)
 
         # ok, above we collated anything with an "ok" on the output side
@@ -305,8 +308,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         if hasattr(op, "imm_data"):
             # select immediate if opcode says so. however also change the latch
             # to trigger *from* the opcode latch instead.
-            op_is_imm = op.imm_data.imm_ok
-            imm = op.imm_data.imm
+            op_is_imm = op.imm_data.ok
+            imm = op.imm_data.data
             self._mux_op(m, sl, op_is_imm, imm, 1)
 
         # create a latch/register for src1/src2 (even if it is a copy of imm)