rename InternalOp to MicrOp

[soc.git] / src / soc / fu / alu / formal / proof_output_stage.py

diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py
index 8148d1eb0177ad2b73437066e04a03c55270af37..7dd3f3833553c75e4536b4b2ff70f94c00d45f7f 100644 (file)
--- a/src/soc/fu/alu/formal/proof_output_stage.py
+++ b/src/soc/fu/alu/formal/proof_output_stage.py
@@ -15,7 +15,7 @@ from nmigen.cli import rtlil
 from soc.fu.alu.output_stage import ALUOutputStage
 from soc.fu.alu.pipe_data import ALUPipeSpec
 from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
 import unittest
 
 
@@ -83,13 +83,13 @@ class Driver(Elaboratable):
             # sigh.  see https://bugs.libre-soc.org/show_bug.cgi?id=305#c61
             # for OP_CMP we do b-a rather than a-b (just like ADD) and
             # then invert the *test condition*.
-            with m.If(rec.insn_type == InternalOp.OP_CMP):
+            with m.If(rec.insn_type == MicrOp.OP_CMP):
                 comb += Assert(cr_out[3] == 1)
             with m.Else():
                 comb += Assert(cr_out[2] == 1)
         with m.Elif(o_signed < 0):
             # ditto as above
-            with m.If(rec.insn_type == InternalOp.OP_CMP):
+            with m.If(rec.insn_type == MicrOp.OP_CMP):
                 comb += Assert(cr_out[2] == 1)
             with m.Else():
                 comb += Assert(cr_out[3] == 1)