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rename regspecs to give a consistent naming scheme
[soc.git]
/
src
/
soc
/
fu
/
branch
/
pipe_data.py
diff --git
a/src/soc/fu/branch/pipe_data.py
b/src/soc/fu/branch/pipe_data.py
index f32872b1d4d49b4f8227ccecdc6088eb454b4067..40633d6d0a35a07df9126501318c1e8b94058b95 100644
(file)
--- a/
src/soc/fu/branch/pipe_data.py
+++ b/
src/soc/fu/branch/pipe_data.py
@@
-23,7
+23,7
@@
op_bctarl CR, TAR, CTR
"""
op_bctarl CR, TAR, CTR
"""
-from nmigen import Signal, Const
+from nmigen import Signal, Const
, Cat
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
from soc.fu.pipe_data import IntegerData, CommonPipeSpec
@@
-33,8
+33,8
@@
from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
class BranchInputData(IntegerData):
regspec = [('SPR', 'spr1', '0:63'),
('SPR', 'spr2', '0:63'),
class BranchInputData(IntegerData):
regspec = [('SPR', 'spr1', '0:63'),
('SPR', 'spr2', '0:63'),
- ('CR', 'cr', '0:3'),
- ('
PC
', 'cia', '0:63')]
+ ('CR', 'cr
_a
', '0:3'),
+ ('
FAST
', 'cia', '0:63')]
def __init__(self, pspec):
super().__init__(pspec)
# Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
def __init__(self, pspec):
super().__init__(pspec)
# Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
@@
-43,30
+43,31
@@
class BranchInputData(IntegerData):
self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
- self.cr
= Signal(4, reset_less=True)
# Condition Register(s) CR0-7
+ self.cr
_a = Signal(4, reset_less=True)
# Condition Register(s) CR0-7
self.cia = Signal(64, reset_less=True) # Current Instruction Address
# convenience variables. not all of these are used at once
self.ctr = self.srr0 = self.hsrr0 = self.spr1
self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr2
self.cia = Signal(64, reset_less=True) # Current Instruction Address
# convenience variables. not all of these are used at once
self.ctr = self.srr0 = self.hsrr0 = self.spr1
self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr2
+ self.cr = self.cr_a
def __iter__(self):
yield from super().__iter__()
yield self.spr1
yield self.spr2
def __iter__(self):
yield from super().__iter__()
yield self.spr1
yield self.spr2
- yield self.cr
+ yield self.cr
_a
yield self.cia
def eq(self, i):
lst = super().eq(i)
return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
yield self.cia
def eq(self, i):
lst = super().eq(i)
return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
- self.cr
.eq(i.cr
), self.cia.eq(i.cia)]
+ self.cr
_a.eq(i.cr_a
), self.cia.eq(i.cia)]
class BranchOutputData(IntegerData):
regspec = [('SPR', 'spr1', '0:63'),
('SPR', 'spr2', '0:63'),
class BranchOutputData(IntegerData):
regspec = [('SPR', 'spr1', '0:63'),
('SPR', 'spr2', '0:63'),
- ('
PC
', 'nia', '0:63')]
+ ('
FAST
', 'nia', '0:63')]
def __init__(self, pspec):
super().__init__(pspec)
self.spr1 = Data(64, name="spr1")
def __init__(self, pspec):
super().__init__(pspec)
self.spr1 = Data(64, name="spr1")
@@
-74,8
+75,8
@@
class BranchOutputData(IntegerData):
self.nia = Data(64, name="nia")
# convenience variables.
self.nia = Data(64, name="nia")
# convenience variables.
- self.
lr = self.ta
r = self.spr1
- self.
ct
r = self.spr2
+ self.
ct
r = self.spr1
+ self.
lr = self.ta
r = self.spr2
def __iter__(self):
yield from super().__iter__()
def __iter__(self):
yield from super().__iter__()
@@
-89,7
+90,11
@@
class BranchOutputData(IntegerData):
self.nia.eq(i.nia)]
self.nia.eq(i.nia)]
-# TODO: replace CompALUOpSubset with CompBROpSubset
class BranchPipeSpec(CommonPipeSpec):
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
opsubsetkls = CompBROpSubset
class BranchPipeSpec(CommonPipeSpec):
regspec = (BranchInputData.regspec, BranchOutputData.regspec)
opsubsetkls = CompBROpSubset
+ def rdflags(self, e): # in order of regspec
+ cr1_en = e.read_cr1.ok # CR A
+ spr1_ok = e.read_spr1.ok # SPR1
+ spr2_ok = e.read_spr2.ok # SPR2
+ return Cat(spr1_ok, spr2_ok, cr1_en, 1) # CIA CR SPR1 SPR2