sorting out bigendian/littleendian including in qemu

[soc.git] / src / soc / fu / compunits / test / test_compunit.py

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index b1ee7c6f2e579e563a5cf36c9b98a18c872ae454..7a73cb83f5f61d29d612b18a0b522e68ff2738ef 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -9,6 +9,7 @@ from soc.decoder.power_enums import Function
 from soc.decoder.isa.all import ISA
 
 from soc.experiment.compalu_multi import find_ok # hack
+from soc.config.test.test_loadstore import TestMemPspec
 
 
 def set_cu_input(cu, idx, data):
@@ -147,12 +148,13 @@ def check_sim_memory(dut, l0, sim, code):
                                  expected_mem, actual_mem))
 
 class TestRunner(FHDLTestCase):
-    def __init__(self, test_data, fukls, iodef, funit):
+    def __init__(self, test_data, fukls, iodef, funit, bigendian):
         super().__init__("run_all")
         self.test_data = test_data
         self.fukls = fukls
         self.iodef = iodef
         self.funit = funit
+        self.bigendian = bigendian
 
     def run_all(self):
         m = Module()
@@ -169,11 +171,13 @@ class TestRunner(FHDLTestCase):
 
         if self.funit == Function.LDST:
             from soc.experiment.l0_cache import TstL0CacheBuffer
-            m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
-                                                    addrwid=3,
-                                                    ifacetype='test_bare_wb')
+            pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
+                                 addr_wid=48,
+                                 mask_wid=8,
+                                 reg_wid=64)
+            m.submodules.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
             pi = l0.l0.dports[0]
-            m.submodules.cu = cu = self.fukls(pi, awid=3)
+            m.submodules.cu = cu = self.fukls(pi, idx=0, awid=3)
             m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
             m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
         else:
@@ -199,7 +203,8 @@ class TestRunner(FHDLTestCase):
                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
                           test.msr,
                           initial_insns=gen, respect_pc=False,
-                          disassembly=insncode)
+                          disassembly=insncode,
+                          bigendian=self.bigendian)
 
                 # initialise memory
                 if self.funit == Function.LDST:
@@ -216,7 +221,7 @@ class TestRunner(FHDLTestCase):
                     print(index, code)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(self.bigendian)  # le / be?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
@@ -283,12 +288,17 @@ class TestRunner(FHDLTestCase):
                     if self.funit == Function.LDST:
                         yield from dump_sim_memory(self, l0, sim, code)
 
-                    yield from self.iodef.check_cu_outputs(res, pdecode2,
-                                                            sim, code)
 
                     # sigh.  hard-coded.  test memory
                     if self.funit == Function.LDST:
                         yield from check_sim_memory(self, l0, sim, code)
+                        yield from self.iodef.check_cu_outputs(res, pdecode2,
+                                                                sim, cu,
+                                                                code)
+                    else:
+                        yield from self.iodef.check_cu_outputs(res, pdecode2,
+                                                                sim, cu.alu,
+                                                                code)
 
 
         sim.add_sync_process(process)