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sorting out bigendian/littleendian including in qemu
[soc.git]
/
src
/
soc
/
fu
/
compunits
/
test
/
test_compunit.py
diff --git
a/src/soc/fu/compunits/test/test_compunit.py
b/src/soc/fu/compunits/test/test_compunit.py
index e1c7a8caf5026ba4ae35c43a998b0a7d5d865c13..7a73cb83f5f61d29d612b18a0b522e68ff2738ef 100644
(file)
--- a/
src/soc/fu/compunits/test/test_compunit.py
+++ b/
src/soc/fu/compunits/test/test_compunit.py
@@
-9,6
+9,7
@@
from soc.decoder.power_enums import Function
from soc.decoder.isa.all import ISA
from soc.experiment.compalu_multi import find_ok # hack
from soc.decoder.isa.all import ISA
from soc.experiment.compalu_multi import find_ok # hack
+from soc.config.test.test_loadstore import TestMemPspec
def set_cu_input(cu, idx, data):
def set_cu_input(cu, idx, data):
@@
-61,6
+62,7
@@
def get_cu_output(cu, idx, code):
def set_cu_inputs(cu, inp):
def set_cu_inputs(cu, inp):
+ print ("set_cu_inputs", inp)
for idx, data in inp.items():
yield from set_cu_input(cu, idx, data)
for idx, data in inp.items():
yield from set_cu_input(cu, idx, data)
@@
-103,8
+105,13
@@
def get_inp_indexed(cu, inp):
res[i] = inp[wrop]
return res
res[i] = inp[wrop]
return res
+def get_l0_mem(l0): # BLECH!
+ if hasattr(l0.pimem, 'lsui'):
+ return l0.pimem.lsui.mem
+ return l0.pimem.mem.mem
+
def setup_test_memory(l0, sim):
def setup_test_memory(l0, sim):
- mem =
l0.mem.mem
+ mem =
get_l0_mem(l0)
print ("before, init mem", mem.depth, mem.width, mem)
for i in range(mem.depth):
data = sim.mem.ld(i*8, 8, False)
print ("before, init mem", mem.depth, mem.width, mem)
for i in range(mem.depth):
data = sim.mem.ld(i*8, 8, False)
@@
-119,8
+126,8
@@
def setup_test_memory(l0, sim):
print (" %6i %016x" % (i, actual_mem))
print (" %6i %016x" % (i, actual_mem))
-def
check
_sim_memory(dut, l0, sim, code):
- mem =
l0.mem.mem
+def
dump
_sim_memory(dut, l0, sim, code):
+ mem =
get_l0_mem(l0)
print ("sim mem dump")
for k, v in sim.mem.mem.items():
print (" %6x %016x" % (k, v))
print ("sim mem dump")
for k, v in sim.mem.mem.items():
print (" %6x %016x" % (k, v))
@@
-129,6
+136,10
@@
def check_sim_memory(dut, l0, sim, code):
actual_mem = yield mem._array[i]
print (" %6i %016x" % (i, actual_mem))
actual_mem = yield mem._array[i]
print (" %6i %016x" % (i, actual_mem))
+
+def check_sim_memory(dut, l0, sim, code):
+ mem = get_l0_mem(l0)
+
for i in range(mem.depth):
expected_mem = sim.mem.ld(i*8, 8, False)
actual_mem = yield mem._array[i]
for i in range(mem.depth):
expected_mem = sim.mem.ld(i*8, 8, False)
actual_mem = yield mem._array[i]
@@
-137,12
+148,13
@@
def check_sim_memory(dut, l0, sim, code):
expected_mem, actual_mem))
class TestRunner(FHDLTestCase):
expected_mem, actual_mem))
class TestRunner(FHDLTestCase):
- def __init__(self, test_data, fukls, iodef, funit):
+ def __init__(self, test_data, fukls, iodef, funit
, bigendian
):
super().__init__("run_all")
self.test_data = test_data
self.fukls = fukls
self.iodef = iodef
self.funit = funit
super().__init__("run_all")
self.test_data = test_data
self.fukls = fukls
self.iodef = iodef
self.funit = funit
+ self.bigendian = bigendian
def run_all(self):
m = Module()
def run_all(self):
m = Module()
@@
-159,14
+171,17
@@
class TestRunner(FHDLTestCase):
if self.funit == Function.LDST:
from soc.experiment.l0_cache import TstL0CacheBuffer
if self.funit == Function.LDST:
from soc.experiment.l0_cache import TstL0CacheBuffer
- m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
- addrwid=3)
- pi = l0.l0.dports[0].pi
- m.submodules.cu = cu = self.fukls(pi, awid=3)
+ pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
+ addr_wid=48,
+ mask_wid=8,
+ reg_wid=64)
+ m.submodules.l0 = l0 = TstL0CacheBuffer(pspec, n_units=1)
+ pi = l0.l0.dports[0]
+ m.submodules.cu = cu = self.fukls(pi, idx=0, awid=3)
m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
else:
m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
else:
- m.submodules.cu = cu = self.fukls()
+ m.submodules.cu = cu = self.fukls(
0
)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
@@
-188,28
+203,34
@@
class TestRunner(FHDLTestCase):
sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
test.msr,
initial_insns=gen, respect_pc=False,
sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
test.msr,
initial_insns=gen, respect_pc=False,
- disassembly=insncode)
+ disassembly=insncode,
+ bigendian=self.bigendian)
# initialise memory
if self.funit == Function.LDST:
yield from setup_test_memory(l0, sim)
index = sim.pc.CIA.value//4
# initialise memory
if self.funit == Function.LDST:
yield from setup_test_memory(l0, sim)
index = sim.pc.CIA.value//4
- while index < len(instructions):
+ while True:
+ try:
+ yield from sim.setup_one()
+ except KeyError: # indicates instruction not in imem: stop
+ break
+ yield Settle()
ins, code = instructions[index]
ins, code = instructions[index]
- yield from sim.setup_one()
- print(code)
+ print(index, code)
# ask the decoder to decode this binary data (endian'd)
# ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(
0) # little / big
?
+ yield pdecode2.dec.bigendian.eq(
self.bigendian) # le / be
?
yield instruction.eq(ins) # raw binary instr.
yield Settle()
yield instruction.eq(ins) # raw binary instr.
yield Settle()
- fn_unit = yield pdecode2.e.fn_unit
+ fn_unit = yield pdecode2.e.
do.
fn_unit
fuval = self.funit.value
self.assertEqual(fn_unit & fuval, fuval)
# set operand and get inputs
yield from set_operand(cu, pdecode2, sim)
fuval = self.funit.value
self.assertEqual(fn_unit & fuval, fuval)
# set operand and get inputs
yield from set_operand(cu, pdecode2, sim)
+ yield Settle()
iname = yield from self.iodef.get_cu_inputs(pdecode2, sim)
inp = get_inp_indexed(cu, iname)
iname = yield from self.iodef.get_cu_inputs(pdecode2, sim)
inp = get_inp_indexed(cu, iname)
@@
-245,9
+266,9
@@
class TestRunner(FHDLTestCase):
# call simulated operation
yield from sim.execute_one()
# call simulated operation
yield from sim.execute_one()
+ yield Settle()
index = sim.pc.CIA.value//4
index = sim.pc.CIA.value//4
- yield Settle()
# get all outputs (one by one, just "because")
res = yield from get_cu_outputs(cu, code)
wrmask = yield cu.wrmask
# get all outputs (one by one, just "because")
res = yield from get_cu_outputs(cu, code)
wrmask = yield cu.wrmask
@@
-264,12
+285,20
@@
class TestRunner(FHDLTestCase):
break
yield
break
yield
- yield from self.iodef.check_cu_outputs(res, pdecode2,
- sim, code)
+ if self.funit == Function.LDST:
+ yield from dump_sim_memory(self, l0, sim, code)
+
# sigh. hard-coded. test memory
if self.funit == Function.LDST:
yield from check_sim_memory(self, l0, sim, code)
# sigh. hard-coded. test memory
if self.funit == Function.LDST:
yield from check_sim_memory(self, l0, sim, code)
+ yield from self.iodef.check_cu_outputs(res, pdecode2,
+ sim, cu,
+ code)
+ else:
+ yield from self.iodef.check_cu_outputs(res, pdecode2,
+ sim, cu.alu,
+ code)
sim.add_sync_process(process)
sim.add_sync_process(process)