use openpower.test.common

[soc.git] / src / soc / fu / compunits / test / test_spr_compunit.py

diff --git a/src/soc/fu/compunits/test/test_spr_compunit.py b/src/soc/fu/compunits/test/test_spr_compunit.py
index 087fc5083130ce3acc12a5eeea1627c40767aaf6..bfc8a50d487e0c58890af2c29f2c3234ce2a6a4f 100644 (file)
--- a/src/soc/fu/compunits/test/test_spr_compunit.py
+++ b/src/soc/fu/compunits/test/test_spr_compunit.py
@@ -1,18 +1,19 @@
 import unittest
-from soc.decoder.power_enums import (XER_bits, Function)
+from openpower.decoder.power_enums import (XER_bits, Function)
 
 from soc.fu.spr.test.test_pipe_caller import get_cu_inputs
-from soc.fu.spr.test.test_pipe_caller import SPRTestCase # creates the tests
+from soc.fu.spr.test.test_pipe_caller import SPRTestCase  # creates the tests
 
-from soc.fu.test.common import ALUHelpers
+from openpower.test.common import ALUHelpers
 from soc.fu.compunits.compunits import SPRFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
+from soc.config.endian import bigendian
 
 
 class SPRTestRunner(TestRunner):
     def __init__(self, test_data):
         super().__init__(test_data, SPRFunctionUnit, self,
-                         Function.SPR)
+                         Function.SPR, bigendian)
 
     def get_cu_inputs(self, dec2, sim):
         """naming (res) must conform to SPRFunctionUnit input regspec
@@ -29,7 +30,7 @@ class SPRTestRunner(TestRunner):
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
-        print ("check extra output", repr(code), cridx_ok, cridx)
+        print("check extra output", repr(code), cridx_ok, cridx)
 
         if rc:
             self.assertEqual(cridx_ok, 1, code)
@@ -44,7 +45,7 @@ class SPRTestRunner(TestRunner):
         yield from ALUHelpers.get_xer_ca(res, alu, dec2)
         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 
-        print ("output", res)
+        print("output", res)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
@@ -53,7 +54,7 @@ class SPRTestRunner(TestRunner):
         yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
 
-        print ("sim output", sim_o)
+        print("sim output", sim_o)
 
         ALUHelpers.check_xer_ov(self, res, sim_o, code)
         ALUHelpers.check_xer_ca(self, res, sim_o, code)
@@ -66,7 +67,7 @@ class SPRTestRunner(TestRunner):
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(SPRTestRunner(SPRTestCase.test_data))
+    suite.addTest(SPRTestRunner(SPRTestCase().test_data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)