+import random
+import unittest
from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
+from nmigen.back.pysim import Simulator, Delay
from nmigen.cli import rtlil
-import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
from soc.decoder.power_decoder import (create_pdecode)
from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function)
-from soc.decoder.selectable_int import SelectableInt
+from soc.decoder.power_enums import XER_bits, Function
from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
+from soc.config.endian import bigendian
+from soc.fu.test.common import (TestCase, ALUHelpers)
from soc.fu.div.pipeline import DivBasePipe
-from soc.fu.div.pipe_data import DivPipeSpec
-import random
+from soc.fu.div.pipe_data import DivPipeSpec, DivPipeKind
+
+
+def log_rand(n, min_val=1):
+ logrange = random.randint(1, n)
+ return random.randint(min_val, (1 << logrange)-1)
+
+
+def get_cu_inputs(dec2, sim):
+ """naming (res) must conform to DivFunctionUnit input regspec
+ """
+ res = {}
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
+ yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
-class TestCase:
- def __init__(self, program, regs, sprs, name):
- self.program = program
- self.regs = regs
- self.sprs = sprs
- self.name = name
+ print("alu get_cu_inputs", res)
+
+ return res
def set_alu_inputs(alu, dec2, sim):
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
# and place it into data_i.b
- reg3_ok = yield dec2.e.read_reg3.ok
- reg1_ok = yield dec2.e.read_reg1.ok
- assert reg3_ok != reg1_ok
- if reg3_ok:
- data1 = yield dec2.e.read_reg3.data
- data1 = sim.gpr(data1).value
- elif reg1_ok:
- data1 = yield dec2.e.read_reg1.data
- data1 = sim.gpr(data1).value
- else:
- data1 = 0
-
- yield alu.p.data_i.a.eq(data1)
-
- # If there's an immediate, set the B operand to that
- reg2_ok = yield dec2.e.read_reg2.ok
- imm_ok = yield dec2.e.imm_data.imm_ok
- if imm_ok:
- data2 = yield dec2.e.imm_data.imm
- elif reg2_ok:
- data2 = yield dec2.e.read_reg2.data
- data2 = sim.gpr(data2).value
- else:
- data2 = 0
- yield alu.p.data_i.b.eq(data2)
-
-
-def set_extra_alu_inputs(alu, dec2, sim):
- carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
- yield alu.p.data_i.xer_ca[0].eq(carry)
- yield alu.p.data_i.xer_ca[1].eq(carry32)
- so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
- yield alu.p.data_i.xer_so.eq(so)
+ inp = yield from get_cu_inputs(dec2, sim)
+ yield from ALUHelpers.set_int_ra(alu, dec2, inp)
+ yield from ALUHelpers.set_int_rb(alu, dec2, inp)
+
+ yield from ALUHelpers.set_xer_so(alu, dec2, inp)
# This test bench is a bit different than is usual. Initially when I
# should have. However, this was really slow, since it needed to
# create and tear down the dut and simulator for every test case.
-# Now, instead of doing that, every test case in ALUTestCase puts some
+# Now, instead of doing that, every test case in DivTestCase puts some
# data into the test_data list below, describing the instructions to
# be tested and the initial state. Once all the tests have been run,
# test_data gets passed to TestRunner which then sets up the DUT and
# massively. Before, it took around 1 minute on my computer, now it
# takes around 3 seconds
-test_data = []
+class DivTestCases:
+ def __init__(self):
+ self.test_data = []
+ for n, v in self.__class__.__dict__.items():
+ if n.startswith("test") and callable(v):
+ self._current_test_name = n
+ v(self)
-class DivTestCase(FHDLTestCase):
- def __init__(self, name):
- super().__init__(name)
- self.test_name = name
+ def run_test_program(self, prog, initial_regs=None, initial_sprs=None):
+ tc = TestCase(prog, self._current_test_name,
+ initial_regs, initial_sprs)
+ self.test_data.append(tc)
- def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
- tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
- test_data.append(tc)
-
- def test_rand(self):
- insns = ["and", "or", "xor"]
+ def tst_0_regression(self):
for i in range(40):
- choice = random.choice(insns)
- lst = [f"{choice} 3, 1, 2"]
+ lst = ["divwo 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- initial_regs[2] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[1] = 0xbc716835f32ac00c
+ initial_regs[2] = 0xcdf69a7f7042db66
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_rand_imm_logical(self):
- insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
- for i in range(10):
- choice = random.choice(insns)
- imm = random.randint(0, (1 << 16)-1)
- lst = [f"{choice} 3, 1, {imm}"]
- print(lst)
- initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ def tst_1_regression(self):
+ lst = ["divwo 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x10000000000000000-4
+ initial_regs[2] = 0x10000000000000000-2
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_cntz(self):
- insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
- for i in range(100):
- choice = random.choice(insns)
- lst = [f"{choice} 3, 1"]
- print(lst)
- initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ def tst_2_regression(self):
+ lst = ["divwo 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xffffffffffff9321
+ initial_regs[2] = 0xffffffffffff7012
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_parity(self):
- insns = ["prtyw", "prtyd"]
- for i in range(10):
- choice = random.choice(insns)
- lst = [f"{choice} 3, 1"]
- print(lst)
- initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ def tst_3_regression(self):
+ lst = ["divwo. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1b8e32f2458746af
+ initial_regs[2] = 0x6b8aee2ccf7d62e9
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_popcnt(self):
- insns = ["popcntb", "popcntw", "popcntd"]
- for i in range(10):
- choice = random.choice(insns)
- lst = [f"{choice} 3, 1"]
- print(lst)
- initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1 << 64)-1)
- self.run_tst_program(Program(lst), initial_regs)
+ def tst_4_regression(self):
+ lst = ["divw 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1c4e6c2f3aa4a05c
+ initial_regs[2] = 0xe730c2eed6cc8dd7
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_popcnt_edge(self):
- insns = ["popcntb", "popcntw", "popcntd"]
- for choice in insns:
- lst = [f"{choice} 3, 1"]
- initial_regs = [0] * 32
- initial_regs[1] = -1
- self.run_tst_program(Program(lst), initial_regs)
+ def tst_5_regression(self):
+ lst = ["divw 3, 1, 2",
+ "divwo. 6, 4, 5"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1c4e6c2f3aa4a05c
+ initial_regs[2] = 0xe730c2eed6cc8dd7
+ initial_regs[4] = 0x1b8e32f2458746af
+ initial_regs[5] = 0x6b8aee2ccf7d62e9
+ self.run_test_program(Program(lst, bigendian), initial_regs)
+
+ def tst_6_regression(self):
+ # CR0 not getting set properly for this one
+ # turns out that overflow is not set correctly in
+ # fu/div/output_stage.py calc_overflow
+ # https://bugs.libre-soc.org/show_bug.cgi?id=425
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x61c1cc3b80f2a6af
+ initial_regs[2] = 0x9dc66a7622c32bc0
+ self.run_test_program(Program(lst, bigendian), initial_regs)
+
+ def tst_7_regression(self):
+ # https://bugs.libre-soc.org/show_bug.cgi?id=425
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0xf1791627e05e8096
+ initial_regs[2] = 0xffc868bf4573da0b
+ self.run_test_program(Program(lst, bigendian), initial_regs)
+
+ def tst_divw_by_zero_1(self):
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x1
+ initial_regs[2] = 0x0
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_cmpb(self):
- lst = ["cmpb 3, 1, 2"]
+ def tst_divw_overflow2(self):
+ lst = ["divw. 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = 0xdeadbeefcafec0de
- initial_regs[2] = 0xd0adb0000afec1de
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[1] = 0x80000000
+ initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_bpermd(self):
- lst = ["bpermd 3, 1, 2"]
- for i in range(20):
+ def tst_divw_overflow3(self):
+ lst = ["divw. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x80000000
+ initial_regs[2] = 0xffffffff
+ self.run_test_program(Program(lst, bigendian), initial_regs)
+
+ def tst_divwuo_regression_1(self):
+ lst = ["divwuo. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x7591a398c4e32b68
+ initial_regs[2] = 0x48674ab432867d69
+ self.run_test_program(Program(lst, bigendian), initial_regs)
+
+ def tst_divwuo_1(self):
+ lst = ["divwuo. 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x50
+ initial_regs[2] = 0x2
+ self.run_test_program(Program(lst, bigendian), initial_regs)
+
+ def test_all(self):
+ instrs = []
+ for width in ("w", "d"):
+ for sign in ("", "u"):
+ for ov in ("", "o"):
+ for cnd in ("", "."):
+ instrs += ["div" + width + sign + ov + cnd,
+ "div" + width + "e" + sign + ov + cnd]
+ for sign in ("s", "u"):
+ instrs += ["mod" + sign + width]
+ test_values = [
+ 0x0,
+ 0x1,
+ 0x2,
+ 0xFFFF_FFFF_FFFF_FFFF,
+ 0xFFFF_FFFF_FFFF_FFFE,
+ 0x7FFF_FFFF_FFFF_FFFF,
+ 0x8000_0000_0000_0000,
+ 0x1234_5678_0000_0000,
+ 0x1234_5678_8000_0000,
+ 0x1234_5678_FFFF_FFFF,
+ 0x1234_5678_7FFF_FFFF,
+ ]
+ for instr in instrs:
+ l = [f"{instr} 3, 1, 2"]
+ for ra in test_values:
+ for rb in test_values:
+ initial_regs = [0] * 32
+ initial_regs[1] = ra
+ initial_regs[2] = rb
+ prog = Program(l, bigendian)
+ self.run_test_program(prog, initial_regs)
+
+ def tst_rand_divwu(self):
+ insns = ["divwu", "divwu.", "divwuo", "divwuo."]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = 1<<random.randint(0,63)
- initial_regs[2] = 0xdeadbeefcafec0de
- self.run_tst_program(Program(lst), initial_regs)
+ initial_regs[1] = log_rand(32)
+ initial_regs[2] = log_rand(32)
+ self.run_test_program(Program(lst, bigendian), initial_regs)
- def test_ilang(self):
- pspec = DivPipeSpec(id_wid=2)
+ def tst_rand_divw(self):
+ insns = ["divw", "divw.", "divwo", "divwo."]
+ for i in range(40):
+ choice = random.choice(insns)
+ lst = [f"{choice} 3, 1, 2"]
+ initial_regs = [0] * 32
+ initial_regs[1] = log_rand(32)
+ initial_regs[2] = log_rand(32)
+ self.run_test_program(Program(lst, bigendian), initial_regs)
+
+
+class TestRunner(unittest.TestCase):
+ def write_ilang(self, div_pipe_kind):
+ pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
alu = DivBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
- with open("logical_pipeline.il", "w") as f:
+ with open(f"div_pipeline_{div_pipe_kind.name}.il", "w") as f:
f.write(vl)
+ def test_write_ilang_div_pipe_core(self):
+ self.write_ilang(DivPipeKind.DivPipeCore)
-class TestRunner(FHDLTestCase):
- def __init__(self, test_data):
- super().__init__("run_all")
- self.test_data = test_data
+ def test_write_ilang_fsm_div_core(self):
+ self.write_ilang(DivPipeKind.FSMDivCore)
- def run_all(self):
+ def test_write_ilang_sim_only(self):
+ self.write_ilang(DivPipeKind.SimOnly)
+
+ def run_all(self, div_pipe_kind):
+ test_data = DivTestCases().test_data
m = Module()
comb = m.d.comb
instruction = Signal(32)
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- pspec = DivPipeSpec(id_wid=2)
+ pspec = DivPipeSpec(id_wid=2, div_pipe_kind=div_pipe_kind)
m.submodules.alu = alu = DivBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
- comb += alu.p.valid_i.eq(1)
comb += alu.n.ready_i.eq(1)
comb += pdecode2.dec.raw_opcode_in.eq(instruction)
sim = Simulator(m)
sim.add_clock(1e-6)
def process():
- for test in self.test_data:
+ for test in test_data:
print(test.name)
program = test.program
- self.subTest(test.name)
- simulator = ISA(pdecode2, test.regs, test.sprs, 0)
- gen = program.generate_instructions()
- instructions = list(zip(gen, program.assembly.splitlines()))
-
- index = simulator.pc.CIA.value//4
- while index < len(instructions):
- ins, code = instructions[index]
-
- print("0x{:X}".format(ins & 0xffffffff))
- print(code)
-
- # ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
- yield instruction.eq(ins) # raw binary instr.
- yield Settle()
- fn_unit = yield pdecode2.e.fn_unit
- self.assertEqual(fn_unit, Function.LOGICAL.value, code)
- yield from set_alu_inputs(alu, pdecode2, simulator)
- yield from set_extra_alu_inputs(alu, pdecode2, simulator)
- yield
- opname = code.split(' ')[0]
- yield from simulator.call(opname)
- index = simulator.pc.CIA.value//4
-
- vld = yield alu.n.valid_o
- while not vld:
+ with self.subTest(test.name):
+ isa_sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
+ test.mem, test.msr,
+ bigendian=bigendian)
+ gen = program.generate_instructions()
+ instructions = list(
+ zip(gen, program.assembly.splitlines()))
+ yield Delay(0.1e-6)
+
+ index = isa_sim.pc.CIA.value//4
+ while index < len(instructions):
+ ins, code = instructions[index]
+
+ print("instruction: 0x{:X}".format(ins & 0xffffffff))
+ print(code)
+ if 'XER' in isa_sim.spr:
+ so = 1 if isa_sim.spr['XER'][XER_bits['SO']] else 0
+ ov = 1 if isa_sim.spr['XER'][XER_bits['OV']] else 0
+ ov32 = 1 if isa_sim.spr['XER'][XER_bits['OV32']] else 0
+ print("before: so/ov/32", so, ov, ov32)
+
+ # ask the decoder to decode this binary data (endian'd)
+ # little / big?
+ yield pdecode2.dec.bigendian.eq(bigendian)
+ yield instruction.eq(ins) # raw binary instr.
+ yield Delay(0.1e-6)
+ fn_unit = yield pdecode2.e.do.fn_unit
+ self.assertEqual(fn_unit, Function.DIV.value)
+ yield from set_alu_inputs(alu, pdecode2, isa_sim)
+
+ # set valid for one cycle, propagate through pipeline...
+ yield alu.p.valid_i.eq(1)
yield
+ yield alu.p.valid_i.eq(0)
+
+ opname = code.split(' ')[0]
+ yield from isa_sim.call(opname)
+ index = isa_sim.pc.CIA.value//4
+
vld = yield alu.n.valid_o
- yield
- alu_out = yield alu.n.data_o.o
- out_reg_valid = yield pdecode2.e.write_reg.ok
- if out_reg_valid:
- write_reg_idx = yield pdecode2.e.write_reg.data
- expected = simulator.gpr(write_reg_idx).value
- print(f"expected {expected:x}, actual: {alu_out:x}")
- self.assertEqual(expected, alu_out, code)
- yield from self.check_extra_alu_outputs(alu, pdecode2,
- simulator, code)
+ while not vld:
+ yield
+ yield Delay(0.1e-6)
+ vld = yield alu.n.valid_o
+ # bug #425 investigation
+ do = alu.pipe_end.div_out
+ ctx_op = do.i.ctx.op
+ is_32bit = yield ctx_op.is_32bit
+ is_signed = yield ctx_op.is_signed
+ quotient_root = yield do.i.core.quotient_root
+ quotient_65 = yield do.quotient_65
+ dive_abs_ov32 = yield do.i.dive_abs_ov32
+ div_by_zero = yield do.i.div_by_zero
+ quotient_neg = yield do.quotient_neg
+ print("32bit", hex(is_32bit))
+ print("signed", hex(is_signed))
+ print("quotient_root", hex(quotient_root))
+ print("quotient_65", hex(quotient_65))
+ print("div_by_zero", hex(div_by_zero))
+ print("dive_abs_ov32", hex(dive_abs_ov32))
+ print("quotient_neg", hex(quotient_neg))
+ print("")
+ yield
+
+ yield Delay(0.1e-6)
+ print("time:", sim._state.timeline.now)
+ yield from self.check_alu_outputs(alu, pdecode2, isa_sim, code)
sim.add_sync_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+ with sim.write_vcd(f"div_simulator_{div_pipe_kind.name}.vcd",
+ f"div_simulator_{div_pipe_kind.name}.gtkw",
traces=[]):
sim.run()
- def check_extra_alu_outputs(self, alu, dec2, sim, code):
- rc = yield dec2.e.rc.data
+ def check_alu_outputs(self, alu, dec2, sim, code):
+
+ rc = yield dec2.e.do.rc.data
+ cridx_ok = yield dec2.e.write_cr.ok
+ cridx = yield dec2.e.write_cr.data
+
+ print("check extra output", repr(code), cridx_ok, cridx)
if rc:
- cr_expected = sim.crl[0].get_range().value
- cr_actual = yield alu.n.data_o.cr0.data
- self.assertEqual(cr_expected, cr_actual, code)
+ self.assertEqual(cridx, 0, code)
+ sim_o = {}
+ res = {}
-if __name__ == "__main__":
- unittest.main(exit=False)
- suite = unittest.TestSuite()
- suite.addTest(TestRunner(test_data))
+ yield from ALUHelpers.get_cr_a(res, alu, dec2)
+ yield from ALUHelpers.get_xer_ov(res, alu, dec2)
+ yield from ALUHelpers.get_int_o(res, alu, dec2)
+ yield from ALUHelpers.get_xer_so(res, alu, dec2)
+
+ print("res output", res)
+
+ yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
+ yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
+ yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
+ yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
- runner = unittest.TextTestRunner()
- runner.run(suite)
+ print("sim output", sim_o)
+
+ ALUHelpers.check_int_o(self, res, sim_o, code)
+ ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
+ ALUHelpers.check_xer_ov(self, res, sim_o, code)
+ ALUHelpers.check_xer_so(self, res, sim_o, code)
+
+ oe = yield dec2.e.do.oe.oe
+ oe_ok = yield dec2.e.do.oe.ok
+ print("oe, oe_ok", oe, oe_ok)
+ if not oe or not oe_ok:
+ # if OE not enabled, XER SO and OV must not be activated
+ so_ok = yield alu.n.data_o.xer_so.ok
+ ov_ok = yield alu.n.data_o.xer_ov.ok
+ print("so, ov", so_ok, ov_ok)
+ self.assertEqual(ov_ok, False, code)
+ self.assertEqual(so_ok, False, code)
+
+ def test_run_div_pipe_core(self):
+ self.run_all(DivPipeKind.DivPipeCore)
+
+ def test_run_fsm_div_core(self):
+ self.run_all(DivPipeKind.FSMDivCore)
+
+ def test_run_sim_only(self):
+ self.run_all(DivPipeKind.SimOnly)
+
+
+if __name__ == "__main__":
+ unittest.main()
projects / soc.git / blobdiff