add random unsigned div tests

[soc.git] / src / soc / fu / div / test / test_pipe_caller.py

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 904cf30b22e20b72edce599f9027fb48534ed293..ba1531128ea76feea3dfebb156cd8e946314a4e8 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -171,6 +171,16 @@ class DIVTestCase(FHDLTestCase):
             initial_regs[2] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_rand_divwu(self):
+        insns = ["divwu", "divwu.", "divwuo", "divwuo."]
+        for i in range(40):
+            choice = random.choice(insns)
+            lst = [f"{choice} 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[2] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_ilang(self):
         pspec = DIVPipeSpec(id_wid=2)
         alu = DIVBasePipe(pspec)