use copy of FHDLTestCase

[soc.git] / src / soc / fu / logical / test / test_countzero.py

diff --git a/src/soc/fu/logical/test/test_countzero.py b/src/soc/fu/logical/test/test_countzero.py
index 43aae01d5302a0458396013ab6fd1ff1e70bf8fc..3a78fd8f339d3a3cdf8a0d529c20c4b9bc222b54 100644 (file)
--- a/src/soc/fu/logical/test/test_countzero.py
+++ b/src/soc/fu/logical/test/test_countzero.py
@@ -2,7 +2,7 @@
 from nmigen import Module, Signal
 from nmigen.cli import rtlil
 from nmigen.back.pysim import Simulator, Delay
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.fu.logical.countzero import ZeroCounter