from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
-
-from soc.logical.pipeline import LogicalBasePipe
-from soc.alu.alu_input_record import CompALUOpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.logical.pipeline import LogicalBasePipe
+from soc.fu.logical.pipe_data import LogicalPipeSpec
import random
self.sprs = sprs
self.name = name
+
def get_rec_width(rec):
recwidth = 0
# Setup random inputs for dut.op
recwidth += width
return recwidth
+
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
yield alu.p.data_i.b.eq(data2)
-
def set_extra_alu_inputs(alu, dec2, sim):
carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- yield alu.p.data_i.carry_in.eq(carry)
+ carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+ yield alu.p.data_i.xer_ca[0].eq(carry)
+ yield alu.p.data_i.xer_ca[1].eq(carry32)
so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
- yield alu.p.data_i.so.eq(so)
-
+ yield alu.p.data_i.xer_so.eq(so)
+
# This test bench is a bit different than is usual. Initially when I
# was writing it, I had all of the tests call a function to create a
def __init__(self, name):
super().__init__(name)
self.test_name = name
+
def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}):
tc = TestCase(prog, initial_regs, initial_sprs, self.test_name)
test_data.append(tc)
choice = random.choice(insns)
lst = [f"{choice} 3, 1, 2"]
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1<<64)-1)
- initial_regs[2] = random.randint(0, (1<<64)-1)
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ initial_regs[2] = random.randint(0, (1 << 64)-1)
self.run_tst_program(Program(lst), initial_regs)
def test_rand_imm_logical(self):
insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
for i in range(10):
choice = random.choice(insns)
- imm = random.randint(0, (1<<16)-1)
+ imm = random.randint(0, (1 << 16)-1)
lst = [f"{choice} 3, 1, {imm}"]
print(lst)
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1<<64)-1)
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
self.run_tst_program(Program(lst), initial_regs)
- @unittest.skip("broken")
def test_cntz(self):
- insns = ["cntlzd", "cnttzd"]
- for i in range(10):
+ insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
+ for i in range(100):
choice = random.choice(insns)
lst = [f"{choice} 3, 1"]
print(lst)
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1<<64)-1)
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
self.run_tst_program(Program(lst), initial_regs)
def test_parity(self):
lst = [f"{choice} 3, 1"]
print(lst)
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1<<64)-1)
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
self.run_tst_program(Program(lst), initial_regs)
def test_popcnt(self):
lst = [f"{choice} 3, 1"]
print(lst)
initial_regs = [0] * 32
- initial_regs[1] = random.randint(0, (1<<64)-1)
+ initial_regs[1] = random.randint(0, (1 << 64)-1)
+ self.run_tst_program(Program(lst), initial_regs)
+
+ def test_popcnt_edge(self):
+ insns = ["popcntb", "popcntw", "popcntd"]
+ for choice in insns:
+ lst = [f"{choice} 3, 1"]
+ initial_regs = [0] * 32
+ initial_regs[1] = -1
self.run_tst_program(Program(lst), initial_regs)
def test_cmpb(self):
initial_regs[2] = 0xd0adb0000afec1de
self.run_tst_program(Program(lst), initial_regs)
+ def test_bpermd(self):
+ lst = ["bpermd 3, 1, 2"]
+ for i in range(20):
+ initial_regs = [0] * 32
+ initial_regs[1] = 1<<random.randint(0,63)
+ initial_regs[2] = 0xdeadbeefcafec0de
+ self.run_tst_program(Program(lst), initial_regs)
+
def test_ilang(self):
- rec = CompALUOpSubset()
+ rec = LogicalPipeSpec.opsubsetkls()
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
alu = LogicalBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("logical_pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = CompALUOpSubset()
+ rec = LogicalPipeSpec.opsubsetkls()
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = LogicalPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
m.submodules.alu = alu = LogicalBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
sim = Simulator(m)
sim.add_clock(1e-6)
+
def process():
for test in self.test_data:
print(test.name)
self.assertEqual(fn_unit, Function.LOGICAL.value, code)
yield from set_alu_inputs(alu, pdecode2, simulator)
yield from set_extra_alu_inputs(alu, pdecode2, simulator)
- yield
+ yield
opname = code.split(' ')[0]
yield from simulator.call(opname)
index = simulator.pc.CIA.value//4
print(f"expected {expected:x}, actual: {alu_out:x}")
self.assertEqual(expected, alu_out, code)
yield from self.check_extra_alu_outputs(alu, pdecode2,
- simulator)
+ simulator, code)
sim.add_sync_process(process)
with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
+ traces=[]):
sim.run()
- def check_extra_alu_outputs(self, alu, dec2, sim):
+
+ def check_extra_alu_outputs(self, alu, dec2, sim, code):
rc = yield dec2.e.rc.data
if rc:
cr_expected = sim.crl[0].get_range().value
- cr_actual = yield alu.n.data_o.cr0
- self.assertEqual(cr_expected, cr_actual)
+ cr_actual = yield alu.n.data_o.cr0.data
+ self.assertEqual(cr_expected, cr_actual, code)
if __name__ == "__main__":
projects / soc.git / blobdiff