sorting out bigendian/littleendian including in qemu
[soc.git] / src / soc / fu / mul / test / test_pipe_caller.py
index cd93e1290117dc388a75b958f1f7e04ebdff68e4..b85c0e04fbdb604f830a39e85a44b9a317423710 100644 (file)
@@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn)
 from soc.decoder.selectable_int import SelectableInt
 from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
-
+from soc.config.endian import bigendian
 
 from soc.fu.test.common import (TestCase, ALUHelpers)
 from soc.fu.mul.pipeline import MulBasePipe
@@ -25,7 +25,6 @@ def get_cu_inputs(dec2, sim):
 
     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
-    yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
     yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
 
     print ("alu get_cu_inputs", res)
@@ -44,7 +43,6 @@ def set_alu_inputs(alu, dec2, sim):
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
 
-    yield from ALUHelpers.set_xer_ca(alu, dec2, inp)
     yield from ALUHelpers.set_xer_so(alu, dec2, inp)
 
 
@@ -78,36 +76,36 @@ class MulTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def tst_0_mullw(self):
+    def test_0_mullw(self):
         lst = [f"mullw 3, 1, 2"]
         initial_regs = [0] * 32
         #initial_regs[1] = 0xffffffffffffffff
         #initial_regs[2] = 0xffffffffffffffff
         initial_regs[1] = 0x2ffffffff
         initial_regs[2] = 0x2
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def tst_1_mullwo_(self):
+    def test_1_mullwo_(self):
         lst = [f"mullwo. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x3b34b06f
         initial_regs[2] = 0xfdeba998
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def tst_2_mullwo(self):
+    def test_2_mullwo(self):
         lst = [f"mullwo 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xffffffffffffa988 # -5678
         initial_regs[2] = 0xffffffffffffedcc # -1234
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def tst_3_mullw(self):
+    def test_3_mullw(self):
         lst = ["mullw 3, 1, 2",
                "mullw 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x6
         initial_regs[2] = 0xe
-        self.run_tst_program(Program(lst), initial_regs)
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_4_mullw_rand(self):
         for i in range(40):
@@ -115,7 +113,7 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_4_mullw_nonrand(self):
         for i in range(40):
@@ -123,9 +121,35 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = i+1
             initial_regs[2] = i+20
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
+
+    def test_mulhw__regression_1(self):
+        lst = ["mulhw. 3, 1, 2"
+              ]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x7745b36eca6646fa
+        initial_regs[2] = 0x47dfba3a63834ba2
+        self.run_tst_program(Program(lst, bigendian), initial_regs)
+
+    def test_4_mullw_rand(self):
+        for i in range(40):
+            lst = ["mullw 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[2] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
-    def tst_rand_mullw(self):
+    def test_rand_mul_lh(self):
+        insns = ["mulhw", "mulhw.", "mulhwu", "mulhwu."]
+        for i in range(40):
+            choice = random.choice(insns)
+            lst = [f"{choice} 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[2] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
+
+    def test_rand_mullw(self):
         insns = ["mullw", "mullw.", "mullwo", "mullwo."]
         for i in range(40):
             choice = random.choice(insns)
@@ -133,7 +157,27 @@ class MulTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[1] = random.randint(0, (1<<64)-1)
             initial_regs[2] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
+
+    def test_rand_mulld(self):
+        insns = ["mulld", "mulld.", "mulldo", "mulldo."]
+        for i in range(40):
+            choice = random.choice(insns)
+            lst = [f"{choice} 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[2] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
+
+    def test_rand_mulhd(self):
+        insns = ["mulhd", "mulhd."]
+        for i in range(40):
+            choice = random.choice(insns)
+            lst = [f"{choice} 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            initial_regs[2] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
 
     def test_ilang(self):
         pspec = MulPipeSpec(id_wid=2)
@@ -172,7 +216,8 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
-                                test.mem, test.msr)
+                                test.mem, test.msr,
+                                bigendian=bigendian)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
                 yield Settle()
@@ -190,7 +235,7 @@ class TestRunner(FHDLTestCase):
                         print ("before: so/ov/32", so, ov, ov32)
 
                     # ask the decoder to decode this binary data (endian'd)
-                    yield pdecode2.dec.bigendian.eq(0)  # little / big?
+                    yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit
@@ -217,7 +262,7 @@ class TestRunner(FHDLTestCase):
                     yield Settle()
 
         sim.add_sync_process(process)
-        with sim.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
+        with sim.write_vcd("mul_simulator.vcd", "mul_simulator.gtkw",
                             traces=[]):
             sim.run()
 
@@ -245,19 +290,16 @@ class TestRunner(FHDLTestCase):
 
         yield from ALUHelpers.get_cr_a(res, alu, dec2)
         yield from ALUHelpers.get_xer_ov(res, alu, dec2)
-        yield from ALUHelpers.get_xer_ca(res, alu, dec2)
         yield from ALUHelpers.get_int_o(res, alu, dec2)
         yield from ALUHelpers.get_xer_so(res, alu, dec2)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
-        yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 
         ALUHelpers.check_int_o(self, res, sim_o, code)
         ALUHelpers.check_xer_ov(self, res, sim_o, code)
-        ALUHelpers.check_xer_ca(self, res, sim_o, code)
         ALUHelpers.check_xer_so(self, res, sim_o, code)
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))