replace data_o with o_data and data_i with i_data as well

[soc.git] / src / soc / fu / spr / test / test_pipe_caller.py

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 8dc13da5c78877a5a0530a6603a3f12483b40b01..fbe2314db96580091989b3ae8fb3c4dcc729bfe7 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -46,7 +46,7 @@ def get_cu_inputs(dec2, sim):
 def set_alu_inputs(alu, dec2, sim):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
 def set_alu_inputs(alu, dec2, sim):
     # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
     # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))

-    # and place it into data_i.b
+    # and place it into i_data.b

 
     inp = yield from get_cu_inputs(dec2, sim)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
 
     inp = yield from get_cu_inputs(dec2, sim)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)


@@ -142,7 +142,7 @@ class TestRunner(unittest.TestCase):
         pspec = SPRPipeSpec(id_wid=2)
         m.submodules.alu = alu = SPRBasePipe(pspec)
 
         pspec = SPRPipeSpec(id_wid=2)
         m.submodules.alu = alu = SPRBasePipe(pspec)
 

-        comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.do)
+        comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do)

         comb += alu.p.valid_i.eq(1)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         comb += alu.p.valid_i.eq(1)
         comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)