from soc.simulator.program import Program
from soc.decoder.isa.all import ISA
from soc.config.endian import bigendian
+from soc.consts import MSR
+
from soc.fu.test.common import (TestCase, ALUHelpers)
from soc.fu.spr.pipeline import SPRBasePipe
"""
res = {}
- yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
- yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
- yield from ALUHelpers.get_sim_slow_spr1(res, sim, dec2) # FAST1
- yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # FAST1
- yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
- yield from ALUHelpers.get_sim_xer_ov(res, sim, dec2) # XER.ov
- yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
+ yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
+ yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
+ yield from ALUHelpers.get_sim_slow_spr1(res, sim, dec2) # FAST1
+ yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # FAST1
+ yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca
+ yield from ALUHelpers.get_sim_xer_ov(res, sim, dec2) # XER.ov
+ yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so
- print ("spr get_cu_inputs", res)
+ print("spr get_cu_inputs", res)
return res
-
def set_alu_inputs(alu, dec2, sim):
# TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
# detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
yield from ALUHelpers.set_fast_spr1(alu, dec2, inp)
yield from ALUHelpers.set_slow_spr1(alu, dec2, inp)
+ return inp
# This test bench is a bit different than is usual. Initially when I
super().__init__(name)
self.test_name = name
- def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
- tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
+ def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
+ initial_msr=0):
+ tc = TestCase(prog, self.test_name, initial_regs, initial_sprs,
+ msr=initial_msr)
self.test_data.append(tc)
def test_1_mfspr(self):
- lst = ["mfspr 1, 26", # SRR0
+ lst = ["mfspr 1, 26", # SRR0
"mfspr 2, 27", # SRR1
"mfspr 3, 8", # LR
- "mfspr 4, 1",] # XER
+ "mfspr 4, 1", ] # XER
initial_regs = [0] * 32
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
'XER': 0xe00c0000}
- self.run_tst_program(Program(lst, bigendian), initial_regs, initial_sprs)
+ self.run_tst_program(Program(lst, bigendian),
+ initial_regs, initial_sprs)
def test_1_mtspr(self):
- lst = ["mtspr 26, 1", # SRR0
- "mtspr 27, 2", # SRR1
+ lst = ["mtspr 26, 1", # SRR0
+ "mtspr 27, 2", # SRR1
"mtspr 1, 3", # XER
- "mtspr 9, 4",] # CTR
+ "mtspr 9, 4", ] # CTR
initial_regs = [0] * 32
initial_regs[1] = 0x129518230011feed
initial_regs[2] = 0x123518230011feed
initial_regs, initial_sprs)
def test_2_mtspr_mfspr(self):
- lst = ["mtspr 26, 1", # SRR0
- "mtspr 27, 2", # SRR1
+ lst = ["mtspr 26, 1", # SRR0
+ "mtspr 27, 2", # SRR1
"mtspr 1, 3", # XER
"mtspr 9, 4", # CTR
- "mfspr 2, 26", # SRR0
- "mfspr 3, 27", # and into reg 2
+ "mfspr 2, 26", # SRR0
+ "mfspr 3, 27", # and into reg 2
"mfspr 4, 1", # XER
- "mfspr 5, 9",] # CTR
+ "mfspr 5, 9", ] # CTR
initial_regs = [0] * 32
initial_regs[1] = 0x129518230011feed
initial_regs[2] = 0x123518230011feed
self.run_tst_program(Program(lst, bigendian),
initial_regs, initial_sprs)
+ @unittest.skip("spr does not have TRAP in it. has to be done another way")
+ def test_3_mtspr_priv(self):
+ lst = ["mtspr 26, 1", # SRR0
+ "mtspr 27, 2", # SRR1
+ "mtspr 1, 3", # XER
+ "mtspr 9, 4", ] # CTR
+ initial_regs = [0] * 32
+ initial_regs[1] = 0x129518230011feed
+ initial_regs[2] = 0x123518230011feed
+ initial_regs[3] = 0xe00c0000
+ initial_regs[4] = 0x1010101010101010
+ initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
+ 'XER': 0x0}
+ msr = 1 << MSR.PR
+ self.run_tst_program(Program(lst, bigendian),
+ initial_regs, initial_sprs, initial_msr=msr)
+
def test_ilang(self):
pspec = SPRPipeSpec(id_wid=2)
alu = SPRBasePipe(pspec)
sim = Simulator(m)
sim.add_clock(1e-6)
+
def process():
for test in self.test_data:
print("test", test.name)
- print ("sprs", test.sprs)
+ print("sprs", test.sprs)
program = test.program
self.subTest(test.name)
sim = ISA(pdecode2, test.regs, test.sprs, test.cr,
- test.mem, test.msr,
- bigendian=bigendian)
+ test.mem, test.msr,
+ bigendian=bigendian)
gen = program.generate_instructions()
instructions = list(zip(gen, program.assembly.splitlines()))
pc = sim.pc.CIA.value
+ msr = sim.msr.value
index = pc//4
while index < len(instructions):
ins, code = instructions[index]
so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
- print ("before: so/ov/32", so, ov, ov32)
+ print("before: so/ov/32", so, ov, ov32)
# ask the decoder to decode this binary data (endian'd)
yield pdecode2.dec.bigendian.eq(bigendian) # little / big?
+ yield pdecode2.msr.eq(msr) # set MSR in pdecode2
+ yield pdecode2.cia.eq(pc) # set PC in pdecode2
yield instruction.eq(ins) # raw binary instr.
yield Settle()
fast_in = yield pdecode2.e.read_fast1.data
spr_in = yield pdecode2.e.read_spr1.data
- print ("dec2 spr/fast in", fast_in, spr_in)
+ print("dec2 spr/fast in", fast_in, spr_in)
fast_out = yield pdecode2.e.write_fast1.data
spr_out = yield pdecode2.e.write_spr.data
- print ("dec2 spr/fast in", fast_out, spr_out)
+ print("dec2 spr/fast in", fast_out, spr_out)
fn_unit = yield pdecode2.e.do.fn_unit
self.assertEqual(fn_unit, Function.SPR.value)
- yield from set_alu_inputs(alu, pdecode2, sim)
+ alu_o = yield from set_alu_inputs(alu, pdecode2, sim)
yield
opname = code.split(' ')[0]
yield from sim.call(opname)
pc = sim.pc.CIA.value
+ msr = sim.msr.value
index = pc//4
print("pc after %08x" % (pc))
sim.add_sync_process(process)
with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
- traces=[]):
+ traces=[]):
sim.run()
def check_alu_outputs(self, alu, dec2, sim, code):
cridx_ok = yield dec2.e.write_cr.ok
cridx = yield dec2.e.write_cr.data
- print ("check extra output", repr(code), cridx_ok, cridx)
+ print("check extra output", repr(code), cridx_ok, cridx)
if rc:
self.assertEqual(cridx, 0, code)
yield from ALUHelpers.get_xer_ca(res, alu, dec2)
yield from ALUHelpers.get_xer_so(res, alu, dec2)
- print ("output", res)
+ print("output", res)
yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
yield from ALUHelpers.get_wr_sim_xer_so(sim_o, sim, alu, dec2)
yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
yield from ALUHelpers.get_wr_slow_spr1(sim_o, sim, dec2)
- print ("sim output", sim_o)
+ print("sim output", sim_o)
ALUHelpers.check_xer_ov(self, res, sim_o, code)
ALUHelpers.check_xer_ca(self, res, sim_o, code)
projects / soc.git / blobdiff