put set_msr and set_cia back in for now

[soc.git] / src / soc / fu / test / common.py

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 39a1fd90e26cfbc1bb7679f97297ae8285ab99ce..a4b9f0e8e7099360079fed7b6997a032cd91634d 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -11,7 +11,8 @@ from soc.regfile.regfiles import FastRegs
 class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
                        msr=0,
-                       do_sim=True):
+                       do_sim=True,
+                       extra_break_addr=None):
 
         self.program = program
         self.name = name
@@ -28,6 +29,7 @@ class TestCase:
         self.mem = mem
         self.msr = msr
         self.do_sim = do_sim
+        self.extra_break_addr = extra_break_addr
 
 
 class ALUHelpers:
@@ -143,10 +145,12 @@ class ALUHelpers:
             yield alu.p.data_i.xer_so.eq(so)
 
     def set_msr(alu, dec2, inp):
+        print ("TODO: deprecate set_msr")
         if 'msr' in inp:
             yield alu.p.data_i.msr.eq(inp['msr'])
 
     def set_cia(alu, dec2, inp):
+        print ("TODO: deprecate set_cia")
         if 'cia' in inp:
             yield alu.p.data_i.cia.eq(inp['cia'])