passing LDSTException over to Trap Pipeline

[soc.git] / src / soc / fu / trap / trap_input_record.py

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index 84715f82b519ab4fc835bd01ac86666422a2eb71..44fd5d6b51f249b19c123571927c56d1799c330e 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -1,9 +1,9 @@
-from nmigen.hdl.rec import Record, Layout
-
+from soc.fu.base_input_record import CompOpSubsetBase
 from soc.decoder.power_enums import (MicrOp, Function)
+from soc.consts import TT
+from soc.experiment.mem_types import LDSTException
 
-
-class CompTrapOpSubset(Record):
+class CompTrapOpSubset(CompOpSubsetBase):
     """CompTrapOpSubset
 
     a copy of the relevant subset information from Decode2Execute1Type
@@ -11,38 +11,16 @@ class CompTrapOpSubset(Record):
     grab subsets.
     """
     def __init__(self, name=None):
-        layout = (('insn_type', MicrOp),
+        layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
+                  ('msr', 64), # TODO: "state" in separate Record
+                  ('cia', 64), # likewise
                   ('is_32bit', 1),
-                  ('traptype', 5), # see trap main_stage.py and PowerDecoder2
+                  ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
                   ('trapaddr', 13),
-                  )
-
-        Record.__init__(self, Layout(layout), name=name)
-
-        # grrr.  Record does not have kwargs
-        self.insn_type.reset_less = True
-        self.insn.reset_less = True
-        self.fn_unit.reset_less = True
-        self.is_32bit.reset_less = True
-        self.traptype.reset_less = True
-        self.trapaddr.reset_less = True
+                  ('ldst_exc', len(LDSTException._exc_types)),
+                  ]
 
-    def eq_from_execute1(self, other):
-        """ use this to copy in from Decode2Execute1Type
-        """
-        res = []
-        for fname, sig in self.fields.items():
-            eqfrom = other.do.fields[fname]
-            res.append(sig.eq(eqfrom))
-        return res
+        super().__init__(layout, name=name)
 
-    def ports(self):
-        return [self.insn_type,
-                self.insn,
-                self.fn_unit,
-                self.is_32bit,
-                self.traptype,
-                self.trapaddr,
-        ]