passing LDSTException over to Trap Pipeline

[soc.git] / src / soc / fu / trap / trap_input_record.py

diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py
index dd87f30ffa6f2bab85b1e957ebd6efba15e5fbec..44fd5d6b51f249b19c123571927c56d1799c330e 100644 (file)
--- a/src/soc/fu/trap/trap_input_record.py
+++ b/src/soc/fu/trap/trap_input_record.py
@@ -1,7 +1,7 @@
 from soc.fu.base_input_record import CompOpSubsetBase
 from soc.decoder.power_enums import (MicrOp, Function)
 from soc.consts import TT
-
+from soc.experiment.mem_types import LDSTException
 
 class CompTrapOpSubset(CompOpSubsetBase):
     """CompTrapOpSubset
@@ -11,7 +11,7 @@ class CompTrapOpSubset(CompOpSubsetBase):
     grab subsets.
     """
     def __init__(self, name=None):
-        layout = (('insn_type', MicrOp),
+        layout = [('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
                   ('msr', 64), # TODO: "state" in separate Record
@@ -19,7 +19,8 @@ class CompTrapOpSubset(CompOpSubsetBase):
                   ('is_32bit', 1),
                   ('traptype', TT.size), # see trap main_stage.py, PowerDecoder2
                   ('trapaddr', 13),
-                  )
+                  ('ldst_exc', len(LDSTException._exc_types)),
+                  ]
 
         super().__init__(layout, name=name)