enable/disable litex irqs based on variant name

[soc.git] / src / soc / litex / florent / libresoc / core.py

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 38c8d008deaebbc214d4bb37ddd7f89c7934472b..3bc76798f64cc170f5672336e17c9169bb774920 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -50,19 +50,33 @@ def get_field(rec, name):
 def make_jtag_ioconn(res, pin, cpupads, iopads):
     (fn, pin, iotype, pin_name, scan_idx) = pin
     #serial_tx__core__o, serial_rx__pad__i,
+    # special-case sdram_clock
+    if pin == 'clock' and fn == 'sdr':
+        cpu = cpupads['sdram_clock']
+        io = iopads['sdram_clock']
+    else:
+        cpu = cpupads[fn]
+        io = iopads[fn]
     print ("cpupads", cpupads)
     print ("iopads", iopads)
     print ("pin", fn, pin, iotype, pin_name)
-    cpu = cpupads[fn]
-    io = iopads[fn]
     print ("cpu fn", cpu)
     print ("io fn", io)
-    sigs = []
-
     name = "%s_%s" % (fn, pin)
+    print ("name", name)
+    sigs = []
 
     if iotype in (IOType.In, IOType.Out):
-        if pin.isdigit():
+        ps = pin.split("_")
+        if pin == 'clock' and fn == 'sdr':
+            cpup = cpu
+            iop = io
+        elif len(ps) == 2 and ps[-1].isdigit():
+            pin, idx = ps
+            idx = int(idx)
+            cpup = getattr(cpu, pin)[idx]
+            iop = getattr(io, pin)[idx]
+        elif pin.isdigit():
             idx = int(pin)
             cpup = cpu[idx]
             iop = io[idx]
@@ -134,7 +148,10 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.interrupt    = Signal(16)
+        irq_en = "noirq" not in variant
+
+        if irq_en:
+            self.interrupt    = Signal(16)
 
         if variant == "standard32":
             self.data_width           = 32
@@ -186,11 +203,12 @@ class LibreSoC(CPU):
             o_memerr_o         = Signal(),   # not connected
             o_pc_o             = Signal(64), # not connected
 
-            # interrupts
-            i_int_level_i      = self.interrupt,
-
         )
 
+        if irq_en:
+            # interrupts
+            self.cpu_params['i_int_level_i'] = self.interrupt
+
         if jtag_en:
             self.cpu_params.update(dict(
                 # JTAG Debug bus
@@ -236,7 +254,7 @@ class LibreSoC(CPU):
             iopads = {}
             litexmap = {}
             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
-                      'pwm', 'sd0'}#, 'sdr'}
+                      'pwm', 'sd0', 'sdr'}
             for periph in subset:
                 origperiph = periph
                 num = None
@@ -248,6 +266,8 @@ class LibreSoC(CPU):
                         periph, num = 'spimaster', None
                     else:
                         periph, num = 'spisdcard', None
+                elif periph == 'sdr':
+                    periph = 'sdram'
                 elif periph == 'mtwi':
                     periph = 'i2c'
                 elif periph == 'sd':
@@ -255,6 +275,12 @@ class LibreSoC(CPU):
                 litexmap[origperiph] = (periph, num)
                 self.cpupads[origperiph] = platform.request(periph, num)
                 iopads[origperiph] = self.pad_cm.request(periph, num)
+                if periph == 'sdram':
+                    # special-case sdram clock
+                    ck = platform.request("sdram_clock")
+                    self.cpupads['sdram_clock'] = ck
+                    ck = self.pad_cm.request("sdram_clock")
+                    iopads['sdram_clock'] = ck
 
             pinset = get_pinspecs(subset=subset)
             p = Pins(pinset)