record commands for building ECP5

[soc.git] / src / soc / litex / florent / ls180soc.py

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 860f820394cc4aae5faa00e4583cbec4433768f7..4279effcffe2fbf15f877e9b2a1b76beab248dac 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -385,7 +385,8 @@ class LibreSoCSim(SoCCore):
                             clk_freq   = sdram_clk_freq)
             #sdrphy_cls = HalfRateGENSDRPHY
             sdrphy_cls = GENSDRPHY
-            self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
+            sdram_pads = self.cpu.cpupads['sdr']
+            self.submodules.sdrphy = sdrphy_cls(sdram_pads)
             #self.submodules.sdrphy = sdrphy_cls(sdram_module,
             #                                       phy_settings,
             #                                       init=ram_init
@@ -409,7 +410,7 @@ class LibreSoCSim(SoCCore):
 
             # SDRAM clock
             sys_clk = ClockSignal()
-            sdr_clk = platform.request("sdram_clock")
+            sdr_clk = self.cpu.cpupads['sdram_clock']
             #self.specials += DDROutput(1, 0, , sdram_clk)
             self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk)
 
@@ -422,11 +423,6 @@ class LibreSoCSim(SoCCore):
         self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
                 tx_fifo_depth = 16,
                 rx_fifo_depth = 16))
-        # "real" pads connect to C4M JTAG iopad
-        uart_pads     = platform.request(uart_name) # "real" (actual) pin
-        uart_io_pads = self.cpu.iopads['uart'] # C4M JTAG pads
-        self.comb += uart_pads.tx.eq(uart_io_pads.tx)
-        self.comb += uart_io_pads.rx.eq(uart_pads.rx)
 
         self.csr.add("uart_phy", use_loc_if_exists=True)
         self.csr.add("uart", use_loc_if_exists=True)
@@ -437,23 +433,28 @@ class LibreSoCSim(SoCCore):
         self.submodules.gpio = GPIOTristateASIC(gpio_core_pads)
         self.add_csr("gpio")
 
-        gpio_pads = platform.request("gpio") # "real" (actual) pins
-        gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads
-        self.comb += gpio_io_pads.i.eq(gpio_pads.i)
-        self.comb += gpio_pads.o.eq(gpio_io_pads.o)
-        self.comb += gpio_pads.oe.eq(gpio_io_pads.oe)
-
         # SPI Master
-        self.submodules.spi_master = SPIMaster(
-            pads         = platform.request("spi_master"),
+        print ("cpupadkeys", self.cpu.cpupads.keys())
+        self.submodules.spimaster = SPIMaster(
+            pads         = self.cpu.cpupads['mspi1'],
             data_width   = 8,
             sys_clk_freq = sys_clk_freq,
             spi_clk_freq = 8e6,
         )
-        self.add_csr("spi_master")
+        self.add_csr("spimaster")
+
+        # SPI SDCard (1 wide)
+        spi_clk_freq = 400e3
+        pads = self.cpu.cpupads['mspi0']
+        spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
+        spisdcard.add_clk_divider()
+        setattr(self.submodules, 'spisdcard', spisdcard)
+        self.add_csr('spisdcard')
 
         # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins
-        self.comb += self.cpu.interrupt[12:16].eq(platform.request("eint"))
+        eintpads = self.cpu.cpupads['eint']
+        print ("eintpads", eintpads)
+        self.comb += self.cpu.interrupt[12:16].eq(eintpads)
 
         # JTAG
         jtagpads = platform.request("jtag")
@@ -473,19 +474,21 @@ class LibreSoCSim(SoCCore):
             self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0])
 
         # PWM
+        pwmpads = self.cpu.cpupads['pwm']
         for i in range(2):
             name = "pwm%d" % i
-            setattr(self.submodules, name, PWM(platform.request("pwm", i)))
+            setattr(self.submodules, name, PWM(pwmpads[i]))
             self.add_csr(name)
 
         # I2C Master
-        self.submodules.i2c = I2CMaster(platform.request("i2c"))
+        i2c_core_pads = self.cpu.cpupads['mtwi']
+        self.submodules.i2c = I2CMaster(i2c_core_pads)
         self.add_csr("i2c")
 
         # SDCard -----------------------------------------------------
 
         # Emulator / Pads
-        sdcard_pads = self.platform.request("sdcard")
+        sdcard_pads = self.cpu.cpupads['sd0']
 
         # Core
         self.submodules.sdphy  = SDPHY(sdcard_pads,
@@ -518,6 +521,8 @@ class LibreSoCSim(SoCCore):
         if not debug:
             return
 
+        jtag_en = ('jtag' in variant) or variant == 'ls180'
+
         # setup running of DMI FSM
         dmi_addr = Signal(4)
         dmi_din = Signal(64)
@@ -801,7 +806,6 @@ def main():
     if args.platform == 'ls180':
         soc = LibreSoCSim(cpu=args.cpu, debug=args.debug,
                           platform=args.platform)
-        soc.add_spi_sdcard()
         builder = Builder(soc, compile_gateware = True)
         builder.build(run         = True)
         os.chdir("../")