add ldst PortInterface misalign unit test (underway)

[soc.git] / src / soc / litex / florent

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index 670638591d786b042f85f3839c59eb92e34ba1e6..b7ed023c21f58bd69da634df258dbca0ece1f4a1 160000 (submodule)
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit 670638591d786b042f85f3839c59eb92e34ba1e6
+Subproject commit b7ed023c21f58bd69da634df258dbca0ece1f4a1