need args to WishboneArbiter, match data width size

[soc.git] / src / soc / minerva / wishbone.py

diff --git a/src/soc/minerva/wishbone.py b/src/soc/minerva/wishbone.py
index 1f56619fac4659a7b7c16417968079fde746470c..2717678654d852ab371a748cf22f037268213fd5 100644 (file)
--- a/src/soc/minerva/wishbone.py
+++ b/src/soc/minerva/wishbone.py
@@ -36,8 +36,8 @@ wishbone_layout = make_wb_layout(32, 4, 32)
 
 
 class WishboneArbiter(Elaboratable):
-    def __init__(self):
-        self.bus = Record(wishbone_layout)
+    def __init__(self, addr_wid=32, mask_wid=4, data_wid=32):
+        self.bus = Record(make_wb_layout(addr_wid, mask_wid, data_wid))
         self._port_map = dict()
 
     def port(self, priority):