significant reorg of the litex pinspecs to use pinmux JSON files

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index f0b2b1bf30344b188198832f1da7b4157f142ec7..fe0a18a1abfe4010c1afc0c340e0e39bef1f8bdf 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -32,14 +32,18 @@ from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.ifetch import ConfigFetchUnit
 from soc.decoder.power_enums import MicrOp
 from soc.debug.dmi import CoreDebug, DMIInterface
+from soc.debug.jtag import JTAG
+from soc.config.pinouts import get_pinspecs
 from soc.config.state import CoreState
 from soc.interrupts.xics import XICS_ICP, XICS_ICS
 from soc.bus.simple_gpio import SimpleGPIO
+from soc.clock.select import ClockSelect, DummyPLL
+
 
 from nmutil.util import rising_edge
 
 
-class TestIssuer(Elaboratable):
+class TestIssuerInternal(Elaboratable):
     """TestIssuer - reads instructions from TestMemory and issues them
 
     efficiency and speed is not the main goal here: functional correctness is.
@@ -77,6 +81,13 @@ class TestIssuer(Elaboratable):
         # DMI interface
         self.dbg = CoreDebug()
 
+        # JTAG interface
+        self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+        if self.jtag_en:
+            subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+                      'pwm', 'sd0'}#, 'sdr'}
+            self.jtag = JTAG(get_pinspecs(subset=subset))
+
         # instruction go/monitor
         self.pc_o = Signal(64, reset_less=True)
         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
@@ -109,6 +120,11 @@ class TestIssuer(Elaboratable):
         m.submodules.core = core = DomainRenamer("coresync")(self.core)
         m.submodules.imem = imem = self.imem
         m.submodules.dbg = dbg = self.dbg
+        if self.jtag_en:
+            m.submodules.jtag = jtag = self.jtag
+            # TODO: UART2GDB mux, here, from external pin
+            # see https://bugs.libre-soc.org/show_bug.cgi?id=499
+            sync += dbg.dmi.connect_to(jtag.dmi)
 
         cur_state = self.cur_state
 
@@ -398,9 +414,14 @@ class TestIssuer(Elaboratable):
     def external_ports(self):
         ports = self.pc_i.ports()
         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
-                  ClockSignal(), ResetSignal(),
                 ]
-        ports += list(self.dbg.dmi.ports())
+
+        if self.jtag_en:
+            ports += list(self.jtag.external_ports())
+        else:
+            # don't add DMI if JTAG is enabled
+            ports += list(self.dbg.dmi.ports())
+
         ports += list(self.imem.ibus.fields.values())
         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 
@@ -419,6 +440,60 @@ class TestIssuer(Elaboratable):
         return list(self)
 
 
+class TestIssuer(Elaboratable):
+    def __init__(self, pspec):
+        self.ti = TestIssuerInternal(pspec)
+        self.pll = DummyPLL()
+        self.clksel = ClockSelect()
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+
+        # TestIssuer runs at internal clock rate
+        m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
+        # ClockSelect runs at PLL output internal clock rate
+        m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
+        m.submodules.pll = pll = self.pll
+
+        # add 2 clock domains established above...
+        cd_int = ClockDomain("intclk")
+        cd_pll = ClockDomain("pllclk")
+        # probably don't have to add cd_int because of DomainRenamer("coresync")
+        m.domains += cd_pll
+
+        # internal clock is set to selector clock-out.  has the side-effect of
+        # running TestIssuer at this speed (see DomainRenamer("intclk") above)
+        comb += cd_int.clk.eq(clksel.core_clk_o)
+
+        # PLL clock established.  has the side-effect of running clklsel
+        # at the PLL's speed (see DomainRenamer("pllclk") above)
+        comb += cd_pll.clk.eq(pll.clk_pll_o)
+
+        # wire up external 24mhz to PLL and clksel
+        comb += clksel.clk_24_i.eq(ClockSignal())
+        comb += pll.clk_24_i.eq(clksel.clk_24_i)
+
+        # now wire up ResetSignals.  don't mind them all being in this domain
+        comb += pll.rst.eq(ResetSignal())
+        comb += clksel.rst.eq(ResetSignal())
+
+        return m
+
+    def ports(self):
+        return list(self.ti.ports()) + list(self.pll.ports()) + \
+               [ClockSignal(), ResetSignal()] + \
+               list(self.clksel.ports())
+
+    def external_ports(self):
+        ports = self.ti.external_ports()
+        #ports.append(ClockSignal())
+        #ports.append(ResetSignal())
+        ports.append(self.clksel.clk_sel_i)
+        ports.append(self.clksel.pll_48_o)
+        return ports
+
+
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,