litex sim.py operational

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index eec494af0094ff170318ab2afa8ff915f662ead1..383afa0d6e8d627b2fdb99f0327d11243fc62faa 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,8 +28,8 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,

-                         nocore=True, # to help test coriolis2 ioring
-                         gpio=False, # for test purposes
+                         #nocore=True, # to help test coriolis2 ioring
+                         gpio=True, # for test purposes

                          debug="jtag", # set to jtag or dmi
                          units=units)
 
                          debug="jtag", # set to jtag or dmi
                          units=units)