set defaults in pspec

[soc.git] / src / soc / simple / test / test_core.py

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 21ffa2e8a0a0e269749f7cf756a96e807b03bd10..9d751cf016eccb5fdf104cea802edb4832dbe59e 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -34,7 +34,7 @@ from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
 from soc.regfile.util import spr_to_fast_reg
 
 
-def setup_regs(core, test):
+def setup_regs(pdecode2, core, test):
 
     # set up INT regfile, "direct" write (bypass rd/write ports)
     intregs = core.regs.int
@@ -49,18 +49,18 @@ def setup_regs(core, test):
     cr = test.cr
     crregs = core.regs.cr
     #cr = int('{:32b}'.format(cr)[::-1], 2)
-    print("cr reg", hex(cr))
+    print("setup cr reg", hex(cr))
     for i in range(8):
         #j = 7-i
         cri = (cr >> (i*4)) & 0xf
         #cri = int('{:04b}'.format(cri)[::-1], 2)
-        print("cr reg", hex(cri), i,
+        print("setup cr reg", hex(cri), i,
               crregs.regs[i].reg.shape())
         yield crregs.regs[i].reg.eq(cri)
 
     # set up XER.  "direct" write (bypass rd/write ports)
     xregs = core.regs.xer
-    print("sprs", test.sprs)
+    print("setup sprs", test.sprs)
     xer = None
     if 'XER' in test.sprs:
         xer = test.sprs['XER']
@@ -112,7 +112,6 @@ def setup_regs(core, test):
     yield Settle()
 
     # XER
-    pdecode2 = core.pdecode2
     so = yield xregs.regs[xregs.SO].reg
     ov = yield xregs.regs[xregs.OV].reg
     ca = yield xregs.regs[xregs.CA].reg