add in predicate mask bit detection when zeroing is enabled
[soc.git] / src / soc / simple / test / test_issuer.py
index ebc529fcada9f0a3b60d2fee463890f477955f21..8694ba927a7ccd058af0623edb8186d210a3f286 100644 (file)
@@ -43,15 +43,15 @@ if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
     # suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))
-    suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
     # suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64))
     suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64))
-    suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64))
     # suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64))
 
     runner = unittest.TextTestRunner()