from nmigen import Module, Signal
from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
import unittest
from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn,
single_bit_flags, Form, SPR,
from soc.decoder.isa.all import ISA
from soc.fu.test.common import TestCase
from soc.simulator.test_sim import DecoderBase
+from soc.config.endian import bigendian
super().__init__(name)
self.test_name = name
- def test_mullw(self):
- lst = [f"addi 1, 0, 0x5678",
- f"addi 2, 0, 0x1234",
- f"mullw 3, 1, 2"]
- self.run_tst_program(Program(lst), [3])
-
- def test_mullw(self):
- lst = [f"addi 1, 0, 0x5678",
- "neg 1, 1",
- f"addi 2, 0, 0x1234",
- f"mullw 3, 1, 2"]
- self.run_tst_program(Program(lst), [3])
+ def tst_mullw(self):
+ lst = ["addi 1, 0, 0x5678",
+ "addi 2, 0, 0x1234",
+ "mullw 3, 1, 2"]
+ self.run_tst_program(Program(lst, bigendian), [3])
+
+ def test_mullwo(self):
+ lst = ["addi 1, 0, 0x5678",
+ "neg 1, 1",
+ "addi 2, 0, 0x1234",
+ "neg 2, 2",
+ "mullwo 3, 1, 2"]
+ self.run_tst_program(Program(lst, bigendian), [3])
def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
initial_mem=None):