sim.add_process(process)
with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[pdecode2.ports()]):
+ traces=pdecode2.ports()):
sim.run()
def test_example(self):
"add 3, 1, 2",
"and 4, 1, 2"]
with Program(lst) as program:
- self.run_test_program(program, [1, 2, 3, 4])
+ self.run_tst_program(program, [1, 2, 3, 4])
def test_ldst(self):
lst = ["addi 1, 0, 0x1234",
"stw 1, 0(2)",
"lwz 3, 0(2)"]
with Program(lst) as program:
- self.run_test_program(program, [1, 2, 3])
+ self.run_tst_program(program, [1, 2, 3])
def test_ldst_extended(self):
lst = ["addi 1, 0, 0x1234",
"stw 1, 0x40(2)",
"lwzx 3, 4, 2"]
with Program(lst) as program:
- self.run_test_program(program, [1, 2, 3])
+ self.run_tst_program(program, [1, 2, 3])
def test_ldst_widths(self):
lst = [" lis 1, 0xdead",
"stb 5, 5(2)",
"ld 5, 0(2)"]
with Program(lst) as program:
- self.run_test_program(program, [1, 2, 3, 4, 5])
+ self.run_tst_program(program, [1, 2, 3, 4, 5])
def test_sub(self):
lst = ["addi 1, 0, 0x1234",
"subfic 4, 1, 0x1337",
"neg 5, 1"]
with Program(lst) as program:
- self.run_test_program(program, [1, 2, 3, 4, 5])
+ self.run_tst_program(program, [1, 2, 3, 4, 5])
- def run_test_program(self, prog, reglist):
+ def run_tst_program(self, prog, reglist):
simulator = InternalOpSimulator()
self.run_tst(prog, simulator)
prog.reset()