tracked down byte-reversal in LDST ISACaller and LDSTCompUnit

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 0b85ca74019f1d44381c9487b54b4ec35aac46fc..63cb5d10327c22683e9423d4ec2f5ad901e53066 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -96,7 +96,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4])
 
-    @unittest.skip("disable")
+    #@unittest.skip("disable")
     def test_ldst(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -111,6 +111,21 @@ class GeneralTestCases(FHDLTestCase):
                                  [1, 2, 3],
                                  initial_mem)
 
+    #@unittest.skip("disable")
+    def test_ldst_update(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "stwu  1, 0(2)",
+               "lwz  3, 0(2)"
+               ]
+        initial_mem = {0x1230: (0x5432123412345678, 8),
+                       0x1238: (0xabcdef0187654321, 8),
+                       }
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program,
+                                 [1, 2, 3],
+                                 initial_mem)
+
     @unittest.skip("disable")
     def test_ld_rev_ext(self):
         lst = ["addi 1, 0, 0x5678",
@@ -131,7 +146,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
-    @unittest.skip("disable")
+    #@unittest.skip("disable")
     def test_ldst_extended(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -254,6 +269,7 @@ class GeneralTestCases(FHDLTestCase):
             program.assembly = '\n'.join(disassembly) + '\n' # XXX HACK!
             self.run_tst_program(program, [1, 3])
 
+    @unittest.skip("disable")
     def test_loop(self):
         """in godbolt.org:
         register unsigned long i asm ("r12");
@@ -272,6 +288,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
+    @unittest.skip("disable")
     def test_30_addis(self):
         lst = [  # "addi 0, 0, 5",
             "addis 12, 0, 0",