also read LDST RM files

[soc.git] / src / soc / sv / trans / svp64.py

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index 79090c9651be46a5a1ecbf7e1ecb6ee5537ba718..0cb14a78d900d99cb8a864de80af77dd7f17d32e 100644 (file)
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -135,7 +135,7 @@ class SVP64RM:
         self.instrs = {}
         pth = find_wiki_dir()
         for fname in os.listdir(pth):
-            if fname.startswith("RM"):
+            if fname.startswith("RM") or fname.startswith("LDSTRM"):
                 for entry in get_csv(fname):
                     self.instrs[entry['insn']] = entry
 
@@ -169,14 +169,9 @@ class SVP64:
                 continue
             opcode = opcode[3:] # strip leading "sv."
 
-            # start working on decoding the svp64 op: sv.baseop/vec2.mode
-            opcode = opcode.split("/") # split at "/"
-            v30b_op = opcode[0]       # first is the v3.0B
-            if len(opcode) == 1:
-                opmodes = [] # no sv modes
-            else:
-                opmodes = opcode[1].split(".") # second splits by dots
-
+            # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
+            opmodes = opcode.split("/") # split at "/"
+            v30b_op = opmodes.pop(0)    # first is the v3.0B
             # check instruction ends with dot
             rc_mode = v30b_op.endswith('.')
             if rc_mode:
@@ -188,9 +183,8 @@ class SVP64:
             if v30b_op not in svp64.instrs:
                 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
                                 (v30b_op, insn))
-            isa.instr[v30b_op].regs[0]
-            v30b_regs = isa.instr[v30b_op].regs[0]
-            rm = svp64.instrs[v30b_op]
+            v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
+            rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
             print ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
             print ("v3.0B regs", opcode, v30b_regs)
             print (rm)
@@ -215,6 +209,8 @@ class SVP64:
                 rfield = rfield.split(";") # s:RA;d:CR1 etc.
                 for r in rfield:
                     rtype = r[0]
+                    # TODO: ignoring s/d makes it impossible to do
+                    # LD/ST-with-update.
                     r = r[2:] # ignore s: and d:
                     svp64_reg_byname[r] = i # this reg in EXTRA position 0-3
                     # check the regtype (if CR, record that)
@@ -598,11 +594,11 @@ if __name__ == '__main__':
                  'sv.cmpi 5, 1, 3, 2',
                  'sv.setb 5, 31',
                  'sv.isel 64.v, 3, 2, 65.v',
-                 'sv.setb/m=r3.sm=1<<r3 5, 31',
+                 'sv.setb/m=r3/sm=1<<r3 5, 31',
                  'sv.setb/vec2 5, 31',
-                 'sv.setb/sw=8.ew=16 5, 31',
+                 'sv.setb/sw=8/ew=16 5, 31',
                  'sv.extsw./ff=eq 5, 31',
-                 'sv.extsw./satu.sz.dz.sm=r3.m=r3 5, 31',
+                 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31',
                  'sv.extsw./pr=eq 5.v, 31',
                 ])
     csvs = SVP64RM()