versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio
authorCole Poirier <colepoirier@gmail.com>
Wed, 21 Oct 2020 21:26:10 +0000 (14:26 -0700)
committerCole Poirier <colepoirier@gmail.com>
Wed, 21 Oct 2020 21:27:45 +0000 (14:27 -0700)
commitaabc5a72500b60117c026e36525afaa313769d7f
treee92bf4a7b1ff3902c35e848faac3ed9298df785a
parent7ee85320fbb58afe83fb1bddf4bbbf229c3814e3
versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio
feature
Makefile
src/soc/litex/florent/libresoc/core.py
src/soc/litex/florent/sim.py
src/soc/simple/issuer_verilog.py