start putting a non-production core together,

sorting the read ports first, to get a look at them

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index b255b7a51e42fcba19f99d638b9ee4c55b3afc28..918f8ea85339ecfebf9fcf802513009fa642ef1a 100644 (file)
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -171,19 +171,19 @@ class RegFile(Elaboratable):
         self._rdports = []
         self._wrports = []
 
-    def read_port(self):
+    def read_port(self, name=None):
         bsz = int(log(self.width) / log(2))
         port = RecordObject([("raddr", bsz),
                              ("ren", 1),
-                             ("data_o", self.width)])
+                             ("data_o", self.width)], name=name)
         self._rdports.append(port)
         return port
 
-    def write_port(self):
+    def write_port(self, name=None):
         bsz = int(log(self.width) / log(2))
         port = RecordObject([("waddr", bsz),
                              ("wen", 1),
-                             ("data_i", self.width)])
+                             ("data_i", self.width)], name=name)
         self._wrports.append(port)
         return port
 

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 12456d25ddb44756b035df3cec303da0b4592ad3..4dfb522a2ebdaa19b77fbe57c3fc7133bdc182c1 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -124,9 +124,10 @@ class SPRRegs(RegFile):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(64, n_sprs)
-        self.w_ports = [self.write_port("dest")]
+        self.w_ports = [self.write_port(name="dest")]
         self.r_ports = [self.read_port("src")]
 
+
 # class containing all regfiles: int, cr, xer, fast, spr
 class RegFiles:
     def __init__(self):

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index ea26a0fea2c88bd52ab803cfc0826bc748533d9b..749d9a8c54abc76ed07fac6a9992863b77190da8 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -1,4 +1,75 @@
-from nmigen import Elaboratable, Module
+"""simple core
+
+not in any way intended for production use.  connects up FunctionUnits to
+Register Files in a brain-dead fashion that only permits one and only one
+Function Unit to be operational.
+"""
+from nmigen import Elaboratable, Module, Signal
+from nmigen.cli import rtlil
 
 from soc.fu.compunits.compunits import AllFunctionUnits
 from soc.regfile.regfiles import RegFiles
+from soc.decoder.power_decoder import create_pdecode
+from soc.decoder.power_decoder2 import PowerDecode2
+
+
+class NonProductionCore(Elaboratable):
+    def __init__(self):
+        self.fus = AllFunctionUnits()
+        self.regs = RegFiles()
+        self.pdecode = pdecode = create_pdecode()
+        self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
+        self.ivalid_i = self.pdecode2.e.valid   # instruction is valid
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+
+        m.submodules.pdecode2 = dec2 = self.pdecode2
+        m.submodules.fus = self.fus
+        self.regs.elaborate_into(m, platform)
+        regs = self.regs
+        fus = self.fus.fus
+
+        # dictionary of lists of regfile read ports
+        byregfiles_rd = {}
+        for (funame, fu) in fus.items():
+            print ("read ports for %s" % funame)
+            for idx in range(fu.n_src):
+                (regfile, regname, wid) = fu.get_in_spec(idx)
+                print ("    %s %s %s" % (regfile, regname, str(wid)))
+                rdflag, read, _ = dec2.regspecmap(regfile, regname)
+                if regfile not in byregfiles_rd:
+                    byregfiles_rd[regfile] = {}
+                # here we start to create "lanes"
+                if idx not in byregfiles_rd[regfile]:
+                    byregfiles_rd[regfile][idx] = []
+                fuspec = (funame, fu, regname, rdflag, read, wid)
+                byregfiles_rd[regfile][idx].append(fuspec)
+
+        # ok just print that out, for convenience
+        for regfile, spec in byregfiles_rd.items():
+            print ("regfile read ports:", regfile)
+            for idx, fuspec in spec.items():
+                print ("  regfile read port %s lane: %d" % (regfile, idx))
+                for (funame, fu, regname, rdflag, read, wid) in fuspec:
+                    print ("    ", funame, regname, wid, read, rdflag)
+                    print ("    ", fu)
+                    print ()
+
+        return m
+
+    def __iter__(self):
+        yield from self.fus.ports()
+        yield from self.pdecode2.ports()
+        # TODO: regs
+
+    def ports(self):
+        return list(self)
+
+
+if __name__ == '__main__':
+    dut = NonProductionCore()
+    vl = rtlil.convert(dut, ports=dut.ports())
+    with open("non_production_core.il", "w") as f:
+        f.write(vl)