git.libre-soc.org Git - soc.git/history - src/soc/regfile/regfiles.py

2020-06-03	Luke Kenneth Casso...	start putting a non-production core together,	blob \| commitdiff \| raw
2020-06-03	Luke Kenneth Casso...	decide to elaborate Refiles into another class, rathe...	blob \| commitdiff \| raw \| diff to current
2020-06-03	Luke Kenneth Casso...	turn RegFiles into module, add all regfiles to it	blob \| commitdiff \| raw \| diff to current
2020-06-03	Tobias Platen	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2020-06-03	Luke Kenneth Casso...	add class containing all regfiles	blob \| commitdiff \| raw \| diff to current
2020-06-02	Luke Kenneth Casso...	whoops cut/paste error, creating write_ports not read_ports	blob \| commitdiff \| raw \| diff to current
2020-05-27	Luke Kenneth Casso...	add extra INT regs port for now, add Fast Regfile	blob \| commitdiff \| raw \| diff to current
2020-05-27	Luke Kenneth Casso...	added XER and CR regfiles, using new VirtualRegPort	blob \| commitdiff \| raw \| diff to current
2020-05-25	Luke Kenneth Casso...	add INT, SPR and CR regfiles	blob \| commitdiff \| raw \| diff to current
2020-05-24	Luke Kenneth Casso...	add stub regfiles.py	blob \| commitdiff \| raw \| diff to current