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update comments on pimem.py
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 6 Oct 2020 19:18:02 +0000
(20:18 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 6 Oct 2020 19:18:02 +0000
(20:18 +0100)
src/soc/experiment/pimem.py
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diff --git
a/src/soc/experiment/pimem.py
b/src/soc/experiment/pimem.py
index e0fadc82c60884381111223f424c2d5676d43177..09d138294c249dfff9aac6beb87dc33331118534 100644
(file)
--- a/
src/soc/experiment/pimem.py
+++ b/
src/soc/experiment/pimem.py
@@
-120,18
+120,18
@@
class PortInterface(RecordObject):
self.priv_mode = Signal() # privileged mode
# mmu
self.priv_mode = Signal() # privileged mode
# mmu
- self.mmu_done = Signal()
- self.mmu_err = Signal()
- self.mmu_invalid = Signal()
+ self.mmu_done = Signal()
# keep for now
+ self.mmu_err = Signal()
# XXX remove: already in LDSTException
+ self.mmu_invalid = Signal()
# XXX remove: already in LDSTException
# radix tree is invalid
# radix tree is invalid
- self.mmu_badtree = Signal()
+ self.mmu_badtree = Signal()
# XXX remove: already in LDSTException
# segment_check fails
# segment_check fails
- self.mmu_segerr = Signal()
+ self.mmu_segerr = Signal()
# XXX remove: already in LDSTException
# permission error takes precedence over RC error
# permission error takes precedence over RC error
- self.mmu_perm_error = Signal()
- self.mmu_rc_error = Signal()
+ self.mmu_perm_error = Signal()
# XXX remove: already in LDSTException
+ self.mmu_rc_error = Signal()
# XXX remove: already in LDSTException
# r.prtbl or r.pid
# r.prtbl or r.pid
- self.mmu_sprval = Signal(64)
+ self.mmu_sprval = Signal(64)
# XXX remove: not needed
# dcache
self.ldst_error = Signal()
# dcache
self.ldst_error = Signal()