adjust PLL connections looking for coriolis2 issue

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index bd87659334ae64c2cf74679109bdfe757fae52a5..2363274cf4f6dcde2dc336297ae16da4f733619e 100644 (file)
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -9,7 +9,6 @@ class DummyPLL(Elaboratable):
         self.instance = instance
         self.clk_24_i = Signal(reset_less=True) # external incoming
         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
-        self.sel_a1_i = Signal(reset_less=True) # PLL selection
         self.clk_pll_o = Signal(reset_less=True)  # output clock
         self.pll_test_o = Signal(reset_less=True)  # test out
         self.pll_vco_o = Signal(reset_less=True) # analog
@@ -18,15 +17,26 @@ class DummyPLL(Elaboratable):
         m = Module()
 
         if self.instance:
-            pll = Instance("pll", i_ref=self.clk_24_i,
-                                  i_a0=self.clk_sel_i[0],
-                                  i_a1=self.clk_sel_i[1],
-                                  o_out_v=self.clk_pll_o,
-                                  o_div_out_test=self.pll_test_o,
-                                  o_vco_test_ana=self.pll_vco_o,
+            clk_24_i = Signal(reset_less=True) # external incoming
+            clk_sel_i = Signal(2, reset_less=True) # PLL selection
+            clk_pll_o = Signal(reset_less=True)  # output clock
+            pll_test_o = Signal(reset_less=True)  # test out
+            pll_vco_o = Signal(reset_less=True) # analog
+            pll = Instance("pll", i_ref=clk_24_i,
+                                  i_a0=clk_sel_i[0],
+                                  i_a1=clk_sel_i[1],
+                                  o_out_v=clk_pll_o,
+                                  o_div_out_test=pll_test_o,
+                                  o_vco_test_ana=pll_vco_o,
                            )
             m.submodules['real_pll'] = pll
             #pll.attrs['blackbox'] = 1
+            m.d.comb += clk_24_i.eq(self.clk_24_i)
+            m.d.comb += clk_sel_i.eq(self.clk_sel_i)
+            m.d.comb += self.clk_pll_o.eq(clk_pll_o)
+            m.d.comb += self.pll_test_o.eq(pll_test_o)
+            m.d.comb += self.pll_vco_o.eq(pll_vco_o)
+
         else:
             m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
             # just get something, stops yosys destroying (optimising) these out
@@ -34,7 +44,6 @@ class DummyPLL(Elaboratable):
                 m.d.comb += self.pll_test_o.eq(self.clk_24_i)
                 m.d.comb += self.pll_vco_o.eq(~self.clk_24_i)
 
-
         return m
 
     def ports(self):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index d8a3d486e358608c3d5bfaf77e0ba841083e642c..c604354ad82a0c26bc09f026a0a04c0641d19c99 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1276,7 +1276,7 @@ class TestIssuer(Elaboratable):
         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
         intclk = ClockSignal("coresync")
         if self.pll_en:
-            comb += intclk.eq(pll.clk_pll_o)
+            comb += intclk.eq(pllclk)
         else:
             comb += intclk.eq(ClockSignal())