explicitly set up a pc_i_ok signal in test_microwatt.py

diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py
index 3ffa9e52c10011648dd5193bbeb20cfbf3ec90ad..ae13cd43d308310cb8ca32e0099516e93d856eb1 100644 (file)
--- a/src/soc/simple/test/test_microwatt.py
+++ b/src/soc/simple/test/test_microwatt.py
@@ -59,6 +59,7 @@ class TestRunner(FHDLTestCase):
         comb = m.d.comb
         go_insn_i = Signal()
         pc_i = Signal(32)
+        pc_i_ok = Signal()
 
         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
                              imem_ifacetype='test_bare_wb',
@@ -74,6 +75,7 @@ class TestRunner(FHDLTestCase):
         l0 = core.l0
 
         comb += issuer.pc_i.data.eq(pc_i)
+        comb += issuer.pc_i.ok.eq(pc_i_ok)
         comb += issuer.go_insn_i.eq(go_insn_i)
 
         # nmigen Simulation
@@ -114,14 +116,14 @@ class TestRunner(FHDLTestCase):
                 yield from setup_regs(core, test)
 
                 yield pc_i.eq(pc)
-                yield issuer.pc_i.ok.eq(1)
+                yield pc_i_ok.eq(1)
 
                 while True:
 
                     # start the instruction
                     yield go_insn_i.eq(1)
                     yield
-                    yield issuer.pc_i.ok.eq(0) # don't change PC from now on
+                    yield pc_i_ok.eq(0) # don't change PC from now on
                     yield go_insn_i.eq(0)      # and don't issue a new insn
                     yield from wait_for_busy_hi(core)
                     yield Settle()