git.libre-soc.org Git - soc.git/history - src/soc/decoder/power_svp64

[soc.git] / src / soc / decoder / power_svp64_rm.py

2021-04-23	Luke Kenneth Casso...	more openpower import conversion	commit \| commitdiff
2021-04-23	Luke Kenneth Casso...	move over to from openpower imports	commit \| commitdiff
2021-03-20	Luke Kenneth Casso...	sort out predicate zeroing in ISACaller	commit \| commitdiff
2021-03-19	Luke Kenneth Casso...	decode predicate src/dest zeroing in SVP64RMModeDecode	commit \| commitdiff
2021-03-17	Luke Kenneth Casso...	add in SVP64 RM Mode decoder	commit \| commitdiff
2021-03-16	Cesar Strauss	Use symbolic values for subfields and bits	commit \| commitdiff
2021-03-16	Cesar Strauss	Define and initialise the mode variable, to be used...	commit \| commitdiff
2021-03-16	Cesar Strauss	Rename class so it does not clash with the enum	commit \| commitdiff
2021-03-15	Cesar Strauss	Fix import	commit \| commitdiff
2021-03-01	Luke Kenneth Casso...	move SVP64 RM decoder to separate module	commit \| commitdiff